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| 型号： | AD73322 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Dual Analog Front End(低成本，低功耗的CMOS通用双模拟前端处理器) |
| 中文描述： | 低成本，低功耗CMOS通用双模拟前端（低成本，低功耗的的CMOS通用双模拟前端处理器） |
| 文件页数： | 11/43页 |
| 文件大小： | 427K |
| 代理商： | AD73322 |
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AD73322
–11–
REV. 0
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
VINP1
VFBP1
Analog Input to the inverting input amplifier on Channel 1’s positive input.
Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator.
Analog Input to the inverting input amplifier on Channel 1’s negative input.
Feedback connection from the output of the inverting amplifier on Channel 1’s negative input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator.
Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent on the status
of Bit 5VEN (CRC:7). As the reference is common to the two codec units, the reference value is set by the wired
OR of the CRC:7 bits in Control Register C of each channel.
A bypass capacitor to AGND2 of 0.1
μ
F is required for the on-chip reference. The capacitor should be fixed to this
pin.
Analog Power Supply Connection.
Analog Ground/Substrate Connection2.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
Serial Clock Output whose rate determines the serial transfer rate to/from the codec. It is used to clock data or
control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the
master clock (MCLK) divided by an integer number—this integer number being the product of the external mas-
ter clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output. Both data and control information may be output on this pin and are clocked on the positive
edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in
three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period be-
fore the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when
SE is low.
Serial Data Input. Both data and control information may be input on this pin and are clocked on the negative
edge of SCLK. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease
power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original
values (before SE was brought low); however, the timing counters and other internal registers are at their reset
values.
Analog Ground/Substrate Connection.
Analog Power Supply Connection.
Analog Output from the Positive Terminal of Output Channel 2.
Analog Output from the Negative Terminal of Output Channel 2.
Analog Output from the Positive Terminal of Output Channel 1.
Analog Output from the Negative Terminal of Output Channel 1.
Analog Input to the inverting input amplifier on Channel 2’s positive input.
Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
Analog Input to the inverting input amplifier on Channel 2’s negative input.
Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.
VINN1
VFBN1
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD
RESET
SCLK
MCLK
SDO
SDOFS
SDIFS
SDI
SE
AGND1
AVDD1
VOUTP2
VOUTN2
VOUTP1
VOUTN1
VINP2
VFBP2
VINN2
VFBN2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322AR | 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73322AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322AR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322ARZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 28SOIC - Trays 制造商:Analog Devices 功能描述:Dual Voice Band Codec 16-Bit 3/5V SOIC28 |
| AD73322ARZ-REEL | 制造商:Analog Devices 功能描述:DUAL VOICE BAND ANALOG FRONT END IC (ROHS) - Tape and Reel 制造商:Analog Devices 功能描述:DUAL VOICEBAND ANALOG FRONT END IC |
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