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参数资料
| 型号： | AD73322 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Dual Analog Front End(低成本，低功耗的CMOS通用双模拟前端处理器) |
| 中文描述： | 低成本，低功耗CMOS通用双模拟前端（低成本，低功耗的的CMOS通用双模拟前端处理器） |
| 文件页数： | 14/43页 |
| 文件大小： | 427K |
| 代理商： | AD73322 |
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AD73322
–14–
REV. 0
GAIN
1
INVERT
SINGLE-ENDED
ENABLE
0/38dB
PGA
DECIMATOR
SERIAL
I/O
PORT
+6/15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
SWITCHED
CAPACITOR
LOW-PASS
FILTER
DIGITAL
SIGMA-
DELTA
MODULATOR
GAIN
6
1
INTER-
POLATOR
V
REF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
DECIMATOR
+6/PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
SWITCHED
CAPACITOR
LOW-PASS
FILTER
DIGITAL
SIGMA-
DELTA
MODULATOR
GAIN
6
1
INTER-
POLATOR
V
REF
VFBN2
VINN2
VINP2
VFBP2
VOUTP2
VOUTN2
AD73322
AGND1
AGND2
DGND
SDOFS
SDO
MCLK
SE
RESET
SCLK
SDIFS
SDI
DVDD
AVDD2
AVDD1
REFERENCE
ANALOG
SIGMA-DELTA
MODULATOR
ANALOG
LOOP
BACK
G1
INVERT
SINGLE-ENDED
ENABLE
0/38dB
PGA
ANALOG
SIGMA-DELTA
MODULATOR
ANALOG
LOOP
BACK
Figure 9. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filter-
ing. Due to the high level of oversampling, the input antialias
requirements are reduced such that a simple single pole RC
stage is sufficient to give adequate attenuation in the band of
interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
Table IV. PGA Settings for the Encoder Channel
IGS2
IGS1
IGS0
Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
6
12
18
20
26
32
38
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322AR | 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73322AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322AR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322ARZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 28SOIC - Trays 制造商:Analog Devices 功能描述:Dual Voice Band Codec 16-Bit 3/5V SOIC28 |
| AD73322ARZ-REEL | 制造商:Analog Devices 功能描述:DUAL VOICE BAND ANALOG FRONT END IC (ROHS) - Tape and Reel 制造商:Analog Devices 功能描述:DUAL VOICEBAND ANALOG FRONT END IC |
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