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| 型号： | AD73322 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Dual Analog Front End(低成本，低功耗的CMOS通用双模拟前端处理器) |
| 中文描述： | 低成本，低功耗CMOS通用双模拟前端（低成本，低功耗的的CMOS通用双模拟前端处理器） |
| 文件页数： | 37/43页 |
| 文件大小： | 427K |
| 代理商： | AD73322 |
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AD73322
–37–
REV. 0
APPENDIX A
Configuring an AD73322 to Operate in Data Mode
1
This section describes a typical sequence of control words that it
would be sent to an AD73322 to set it up for data mode opera-
tion. It is not intended to be a definitive initialization sequence,
but will show users the typical input/output events that occur in
the programming and operation phases
2
. This description panel
refers to Figure 43.
In Step 1, we have the first output sample event following device
reset. The SDOFS signal is raised on both channels simulta-
neously, which prepares the DSP Rx register to accept the ADC
word from Channel 2, while SDOFS from Channel 1 becomes
an SDIFS to Channel 2. As the SDOFS of Channel 2 is coupled
to the DSP’s TFS and RFS, and to the SDIFS of Channel 1,
this event also forces a new control word to be output from the
DSP Tx register to Channel 1.
In Step 2, we observe the status of the channels following the
transmission of the first control word. The DSP has received the
ADC word from Channel 2, while Channel 2 has received the
ADC word from Channel 1 and Channel 1 has received the
Control word destined for Channel 2. At this stage, the SDOFS
of both channels are again raised because Channel 2 has received
Channel 1’s ADC word, and as it is not a valid control word
addressed to Channel 2, it is passed on to the DSP. Likewise,
Channel 1 has received a control word destined for Channel 2—
address field is not zero—and it decrements the address field of
the control word and passes it on.
Step 3 shows completion of the first series of control word
writes. The DSP has now received both invalid ADC words and
each channel has received a control word that addresses control
register B and sets the internal MCLK divider ratio to 1, SCLK
rate to DMCLK/8. Note that both channels are updated simul-
taneously as both receive the addressed control word at the same
time. This is an important factor in cascaded operation as any
latency between updating the SCLK or DMCLK of channels
can result in corrupted operation. This will not happen in the
case of an FSLB configuration as shown here, but must be taken
into account in a non-FSLB configuration. One other important
observation of this sequence is that the data words
are received and transmitted in reverse order, i.e., the ADC
words are received by the DSP, Channel 2 first, then Channel 1,
and, similarly the transmit words from the DSP are sent Channel
2 first, then Channel 1. This ensures that all channels are up-
dated at the same time.
In Step 4, the next ADC sample event that happens raises the
SDOFS lines of each of the channels. The DSP Tx register
contains the first of the two control words to be written to the
cascade—the word for Channel 2.
In Step 5, following transmission of the first of the two control
words, the DSP Rx register contains Channel 2’s ADC word,
Channel 2’s serial register contains the Channel 1 ADC word,
Channel 1’s serial register contains the control word addressed
to Channel 2 and the DSP Tx register contains the next control
word—that addressed to Channel 1. Again, both channels raise
their SDOFS lines as both have received control words not
addressed to them.
Step 6 shows the completion of the second set of control word
writes. In this case, both channels have received a control word
addressed to control register A, which sets the device count field
equal to two channels in cascade and sets the
PGM
/DATA bit
to one to put the channel in data mode.
In Step 7, the programming phase is complete and we now
begin actual channel data read and write. The words loaded into
the serial registers of the two channels at the ADC sampling
event now contain valid ADC data and the words written to the
channels from the DSP’s Tx register will now be interpreted as
DAC words. Note, therefore, that the DSP Tx register contains
the DAC word for Channel 2.
In Step 8, the first DAC word has been transmitted into the
cascade and the ADC word from Channel 2 has been read from
the cascade. The DSP Tx register now contains the DAC word
for Channel 1. As the words being sent to the cascade are now
being interpreted as 16-bit DAC words, the addressing scheme
now changes from one where the address was embedded in the
transmitted word to one where the serial port now counts the
SDIFS pulses. When the number of SDIFS pulses received
equals the value in the channel count field of control register
A—the length of the cascade—each channel updates its DAC
register with the present word in its serial register. In Step 8
each channel has received only one SDIFS pulse; Channel 2
received one SDIFS from the SDOFS of Channel 1 when it
sent its ADC word and Channel 1 received one SDIFS pulse
when it received the DAC word for Channel 2 from the DSP’s
Tx register. Therefore, each channel raises its SDOFS line to
pass on the current word in its serial register, and each channel
now receives another SDIFS pulse.
Step 9 shows the completion of an ADC read and DAC write
cycle. Following Step 8, each channel has received two SDIFS
pulses that equal the setting of the channel count field in Con-
trol Register A. The DAC register in each channel is now
updated with the contents of the word that accompanied the
SDIFS pulse that satisfied the channel count requirement. The
internal frame sync counter is now reset to zero and will begin
counting for the next DAC update cycle.
NOTES
1
Channel 1 and Channel 2 of the description refer to the two AFE sections of
the AD73322 device.
2
This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure that there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Register B as it contains settings for SCLK and DMCLK
rates.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322AR | 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73322AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322AR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322ARZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 28SOIC - Trays 制造商:Analog Devices 功能描述:Dual Voice Band Codec 16-Bit 3/5V SOIC28 |
| AD73322ARZ-REEL | 制造商:Analog Devices 功能描述:DUAL VOICE BAND ANALOG FRONT END IC (ROHS) - Tape and Reel 制造商:Analog Devices 功能描述:DUAL VOICEBAND ANALOG FRONT END IC |
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