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参数资料
型号： AD73322
厂商： Analog Devices, Inc.
英文描述： Low Cost, Low Power CMOS General Purpose Dual Analog Front End(低成本，低功耗的CMOS通用双模拟前端处理器)
中文描述： 低成本，低功耗CMOS通用双模拟前端（低成本，低功耗的的CMOS通用双模拟前端处理器）
文件页数： 2/43页
文件大小： 427K
代理商： AD73322
–2–
REV. 0
AD73322–SPECIFICATIONS
1
AD73322A
Typ
Parameter
Min
Max
Units
Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, V
REFOUT
Minimum Load Resistance
Maximum Load Capacitance
INPUT AMPLIFIER
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
ADC SPECIFICATIONS
Maximum Input Range at VIN
2, 3
5VEN = 0
1.08
1.2
50
1.32
V
ppm/
°
C 0.1
μ
F Capacitor Required from
REFCAP to AGND2
V
Unloaded
k
pF
130
1.2
1.08
1
1.32
100
±
1.0
1.578
50
100
mV
V
pF
Max Output Swing = (1.578/1.2)
×
VREFCAP
f
C
= 32 kHz
+1
–1
5
±
1.0
1.0
0.5
V
V
Bits
%
μ
s
μ
s
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
5VEN = 0
Measured Differentially
Max Input = (1.578/1.2)
×
VREFCAP
Measured Differentially
1.578
–2.85
1.0954
–6.02
V p-p
dBm
V p-p
dBm
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
–0.5
–1.5
0.4
–0.7
±
0.1
+1.2
+0.1
dB
dB
dB
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 5
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
300 Hz to 3400 Hz; f
SAMP
= 8 kHz
0 Hz to f
SAMP
/2; f
SAMP
= 64 kHz
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
72
78
78
57
56
dB
dB
dB
dB
55
52
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk
–84
–70
–65
–71
–100
–73
–60
dB
dB
dB
dBm0
dB
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
ADC-to-DAC
ADC-to-ADC
–100
dB
–70
+10
–65
dB
mV
dB
DC Offset
Power Supply Rejection
–30
+45
Group Delay
4, 5
Input Resistance at PGA
2, 4, 6
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
25
20
μ
s
k
Input Amplifiers Bypassed
+1
–1
16
25
100
Bits
μ
s
μ
s
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
(AVDD = +3 V
6
10%; DVDD = +3 V
6
10%; DGND = AGND = 0 V, f
MCLK
=
16.384 MHz, f
SAMP
= 64 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
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