参数资料
| 型号： | AD73322LYRZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/48页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG FRONT END DUAL 28-SOIC |
| 标准包装： | 27 |
| 位数： | 16 |
| 通道数： | 4 |
| 功率（瓦特）： | 73mW |
| 电压 - 电源，模拟： | 2.7 V ~ 5.5 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.5 V |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
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AD73322L
Rev. A | Page 11 of 48
Mnemonic
Function
SCLK
Serial Clock Output. This rate determines the serial transfer rate to/from the codec. It is used to clock data or control
information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK)
divided by an integer number—this integer number being the product of the external master clock rate divider and the serial
clock rate divider.
MCLK
Master Clock Input. MCLK is driven from an external clock signal.
SDO
Serial Data Output. Both data and control information may be output on this pin and are clocked on the positive edge of
SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFS
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period before the first
bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low.
SDIFS
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period before the first bit
(MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low.
SDI
Serial Data Input. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK.
SDI is ignored when SE is low.
SE
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are
three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is
brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however,
the timing counters and other internal registers are at their reset values.
AGND1
Analog Ground/Substrate Connection.
AVDD1
Analog Power Supply Connection.
VOUTP2
Analog Output from the Positive Terminal of Output Channel 2.
VOUTN2
Analog Output from the Negative Terminal of Output Channel 2.
VOUTP1
Analog Output from the Positive Terminal of Output Channel 1.
VOUTN1
Analog Output from the Negative Terminal of Output Channel 1.
VINP2
Analog Input to the inverting input amplifier on Channel 2’s positive input.
VFBP2
Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input amplifiers are
bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
VINN2
Analog Input to the inverting input amplifier on Channel 2’s negative input.
VFBN2
Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input amplifiers are
bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LYST | 制造商:Analog Devices 功能描述: |
| AD73322LYSTZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD73360 | 制造商:AD 制造商全称:Analog Devices 功能描述:Six-Input Channel Analog Front End |
| AD73360AR | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD73360AR-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 5V/5V/5V 28SOIC W - Tape and Reel |
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