参数资料
| 型号： | AD73322LYRZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/48页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG FRONT END DUAL 28-SOIC |
| 标准包装： | 27 |
| 位数： | 16 |
| 通道数： | 4 |
| 功率（瓦特）： | 73mW |
| 电压 - 电源，模拟： | 2.7 V ~ 5.5 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.5 V |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
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AD73322L
Rev. A | Page 12 of 48
TERMINOLOGY
Absolute Gain
A measure of converter gain for a known signal. Absolute gain
is measured (differentially) with a 1 kHz sine wave at 0 dBm0
for the DAC and with a 1 kHz sine wave at 0 dBm0 for the
ADC. The absolute gain specification is used for gain tracking
error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude
of the coupled signal to the amplitude of the input signal.
Crosstalk is expressed in dB.
Gain Tracking Error
Measures changes in converter output for different signal levels
relative to an absolute signal level. The absolute signal level is
0 dBm0 (equal to absolute gain) at 1 kHz for the DAC and 0
dBm0 (equal to absolute gain) at 1 kHz for the ADC. Gain
tracking error at 0 dBm0 (ADC) and 0 dBm0 (DAC) is 0 dB
by definition.
Group Delay
The derivative of radian phase with respect to radian frequency,
d(f)/df. Group delay is a measure of the average delay of a
system as a function of frequency. A linear system with a
constant group delay has a linear phase response. The deviation
of group delay from a constant indicates the degree of nonlinear
phase response of the system.
Idle Channel Noise
The total signal energy measured at the output of the device
when the input is grounded (measured in the frequency range
300 Hz to 3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second-
order terms include (fa + fb) and (fa fb), while the third-order
terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
Power Supply Rejection
Measures the susceptibility of a device to noise on the power
supply. Power supply rejection is measured by modulating the
power supply with a sine wave and measuring the noise at the
output (relative to 0 dB).
Sample Rate
The rate at which the ADC updates its output register and the
DAC updates its output from its input register. The sample rate
can be chosen from a list of four that are fixed relative to the
DMCLK. Sample rate is set by programming bits DIR0-1 in
Control Register B of each channel.
SNR + THD
Signal-to-noise ratio plus harmonic distortion is the ratio of the
rms value of the measured input signal to the rms sum of all
other spectral components in the frequency range 300 Hz to
3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
Table 7.
Abbreviation
Definition
ADC
Analog-to-digital converter.
AFE
Analog front end.
AGT
Analog gain tap.
ALB
Analog loop-back.
BW
Bandwidth.
CRx
A control register where x is a placeholder for
an alphabetic character (A to H). There are eight
read/write control registers on the AD73322L—
CRA through CRH.
CRx:n
A bit position, where n is a placeholder for a
numeric character (0 to 7), within a control
register, where x is a placeholder for an
alphabetic character (A to E). Position 7
represents the MSB and Position 0 represents
the LSB.
DAC
Digital-to-analog converter.
DGT
Digital gain tap.
DLB
Digital loop-back.
DMCLK
Device (internal) master clock. This is the
internal master clock resulting from the
external master clock (MCLK) being divided by
the on-chip master clock divider.
FS
Full scale.
FSLB
Frame sync loop-back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of nonFSLB,
SDOFS and SDO are connected to the Rx port of
the DSP while SDIFS and SDI are connected to
the Tx port.
PGA
Programmable gain amplifier.
SC
Switched capacitor.
SLB
SPORT loop-back.
SNR
Signal-to-noise ratio.
SPORT
Serial port.
THD
Total harmonic distortion.
VBW
Voice bandwidth.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LYST | 制造商:Analog Devices 功能描述: |
| AD73322LYSTZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD73360 | 制造商:AD 制造商全称:Analog Devices 功能描述:Six-Input Channel Analog Front End |
| AD73360AR | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD73360AR-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 5V/5V/5V 28SOIC W - Tape and Reel |
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