参数资料
| 型号： | AD73322LYRZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 45/48页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG FRONT END DUAL 28-SOIC |
| 标准包装： | 27 |
| 位数： | 16 |
| 通道数： | 4 |
| 功率（瓦特）： | 73mW |
| 电压 - 电源，模拟： | 2.7 V ~ 5.5 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.5 V |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
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AD73322L
Rev. A | Page 6 of 48
A and Y Versions
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
0.0625
0.25
dB
0.125
0.6
dB
0.1875
1.4
dB
0.25
2.8
dB
0.3125
4.5
dB
0.375
7.0
dB
0.4375
9.5
dB
> 0.5
<12.5
dB
LOGIC INPUTS
VINH, Input High Voltage
DVDD
0.8
DVDD
V
VINL, Input Low Voltage
0
0.8
V
IIH, Input Current
10
+10
A
CIN, Input Capacitance
10
pF
LOGIC OUTPUT
VOH, Output High Voltage
DVDD
0.4
DVDD
V
|IOUT| ≤100 A
VOL, Output Low Voltage
0
0.4
V
|IOUT| ≤100 A
Three-State Leakage Current
10
+10
A
POWER SUPPLIES
AVDD1, AVDD2
2.7
3.3
V
2.7
3.3
V
DVDD IDD9
See Table 2
1 Test conditions: input PGA set for 0 dB gain, output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
2 At input to sigma-delta modulator of ADC.
3 Guaranteed by design.
4 Overall group delay is affected by the sample rate and the external digital filtering.
5 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by (3/3 × 1011)/DMCLK.
6 Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
7 At VOUT output.
8 Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of 10 dBm0), with 38 dB
preamplifier bypassed and input gain of 0 dB.
9 Test conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.
CURRENT SUMMARY
AVDD = DVDD = 3.3 V. These values are in mA and are typical values unless otherwise noted.
Table 2.
Conditions
Analog
Current
Digital
Current
Total
Current (Typ)
Total
Current (Max)
SE
MCLK ON
Comments
ADCs on only
3.4
6.3
9.7
12
1
YES
REFOUT disabled
DACs on only
8.8
6.5
15.3
20
1
YES
REFOUT disabled
ADCs and DACs on
11.6
7.0
18.6
23
1
YES
REFOUT disabled
ADCs and DACs and
Input amps on
13.8
7.0
20.8
26
1
YES
REFOUT disabled
ADCs and DACs and
AGT on
13.2
7.0
20.2
26
1
YES
REFOUT disabled
All sections on
17.2
7.0
24.2
31
1
YES
REFCAP on only
0.65
0
0.67
1.25
0
NO
REFOUT disabled
REFCAP and REFOUT
On only
2.56
0
2.57
4.5
0
NO
All sections off
0
1.25
1.8
0
YES
MCLK active levels equal
to 0 V and DVDD
All sections off
0 A
12.5 A
12.7 A
40 A
0
NO
Digital inputs static and
Equal to 0 V or DVDD
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