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参数资料
| 型号： | AD73422 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer(带DSP微计算机的双模拟前端) |
| 中文描述： | 双低功耗CMOS模拟前端（带DSP的微计算机的双模拟前端与DSP的微机） |
| 文件页数： | 11/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422 |
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REV. 0
AD73422
–
11
–
Table I. PGA Settings for the Encoder Channel
IGS2
IGS1
IGS0
Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
6
12
18
20
26
32
38
ADC
Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decima-
tion filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73422’s input channels employ a sigma-delta conver-
sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling where the sampling rate is many times the highest
frequency of interest. In the case of the AD73422, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to F
S
/2 = DMCLK/16
(Figure 4a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 4b). The combination
BAND
OF
INTEREST
F
/2
DMCLK/16
a.
F
/2
DMCLK/16
NOISE-SHAPING
b.
BAND
OF
INTEREST
F
S
/2
DMCLK/16
DIGITAL FILTER
BAND
OF
INTEREST
c.
Figure 4. Sigma-Delta Noise Reduction
of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 4c).
Figure 5 shows the various stages of filtering that are employed
in a typical AD73422 application. In Figure 5a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling fre-
quency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 5b,
the signal and noise-shaping responses of the sigma-delta modu-
lator are shown. The signal response provides further rejection
of any high frequency signals, while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 5c shows the response of the digital decima-
tion filter (Sinc-cubed response) with nulls every multiple of
DMCLK/256, which corresponds to the decimation filter up-
date rate for a 64 kHz sampling. The nulls of the Sinc3 response
correspond with multiples of the chosen sampling frequency.
The final detail in Figure 5d shows the application of a final
antialias filter in the DSP engine. This has the advantage of
being implemented according to the user’s requirements and
available MIPS. The filtering in Figures 5a through 5c is imple-
mented in the AD73422.
F
B
= 4kHz
a. Analog Antialias Filter Transfer Function
F
SINIT
= DMCLK/8
F
B
= 4kHz
F
SINIT
= DMCLK/8
NOISE TRANSFER FUNCTION
SIGNAL TRANSFER FUNCTION
b. Analog Sigma-Delta Modulator Transfer Function
F
B
= 4kHz
c. Digital Decimator Transfer Function
F
SINTER
= DMCLK/256
F
B
= 4kHz
d. Final Filter LPF (HPF) Transfer Function
Figure 5. ADC Frequency Responses
F
SINTER
= DMCLK/256
F
SFINAL
= 8kHz
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