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参数资料
| 型号： | AD73422 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer(带DSP微计算机的双模拟前端) |
| 中文描述： | 双低功耗CMOS模拟前端（带DSP的微计算机的双模拟前端与DSP的微机） |
| 文件页数： | 19/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422 |
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REV. 0
AD73422
–
19
–
OPERATION
Resetting the AD73422’s AFE
The pin
ARESET
resets all the control registers. All registers are
reset to zero indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the
ARESET
pin, the
device can be reset using the RESET bit (CRA:7) in Control
Register A. Both hardware and software resets require four
DMCLK cycles. On reset, DATA/
PGM
(CRA:0) is set to 0
(default condition) thus enabling Program Mode. The reset
conditions ensure that the device must be programmed to the
correct settings after power-up or reset. Following a reset, the
SDOFS will be asserted 2048 DMCLK cycles after
ARESET
going high. The data that is output following reset and during
Program Mode is random and contains no valid information
until either data or mixed mode is set.
Power Management
The individual functional blocks of the AD73422 can be en-
abled separately by programming the power control register
CRC. It allows certain sections to be powered down if not re-
quired, which adds to the device’s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. The power
control registers provides individual control settings for the
major functional blocks on each codec unit and also a global
override that allows all sections to be powered up by setting the
bit. Using this method the user could, for example, individually
enable a certain section, such as the reference (CRC:5), and
disable all others. The global power-up (CRC:0) can be used to
enable all sections but if power-down is required using the glo-
bal control, the reference will still be enabled, in this case, be-
cause its individual bit is set. Refer to Table XIII for details of
the settings of CRC.
NOTE: As both codec units share a common reference, the
reference control bits (CRC:5–7) in each SPORT are wire ORed
to allow either device to control the reference. Hence the refer-
ence is only in a reset state when the relevant control bit of both
codec units is set to 0.
AFE Operating Modes
There are three main modes of operation available on the
AD73422; Program, Data and Mixed Program/Data modes.
There are also two other operating modes which are typically
reserved as diagnostic modes: Digital and SPORT Loopback.
The device configuration—register settings—can be changed
only in Program and Mixed Program/Data Modes. In all modes,
transfers of information to or from the device occur in 16-bit
packets, therefore the DSP engine’s SPORT will be programmed
for 16-bit transfers.
Program (Control) Mode
In Program Mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation—SPORT
operation, cascade length, power management, input/output
gain, etc. In this mode, the 16-bit information packet sent to the
device by the DSP engine is interpreted as a control word whose
format is shown in Table X. In this mode, the user must address
the device to be programmed using the address field of the con-
trol word. This field is read by the device and if it is zero (000 bin)
then the device recognizes the word as being addressed to it. If the
address field is not zero, it is then decremented and the control
word is passed out of the device—either to the next device in a
cascade or back to the DSP engine. This 3-bit address format
allows the user to uniquely address any one of up to eight de-
vices in a cascade; please note that this addressing scheme is
valid only in sending control information to the device—a differ-
ent format is used to send DAC data to the device(s). As the
AD73422 features a dual AFE, these two channels have sepa-
rate device addresses for programming purposes—the two de-
vice addresses correspond to 0 and 1.
Following reset, when the SE pin is enabled, the codec responds
by raising the SDOFS pin to indicate that an output sample
event has occurred. Control words can be written to the device
to coincide with the data being sent out of the SPORT or they
can lag the output words by a time interval that should not
exceed the sample interval. After reset, output frame sync pulses
will occur at a slower default sample rate, which is DMCLK/
2048, until Control Register B is programmed after which the
SDOFS pulses will revert to the DMCLK/256 rate. During
Program Mode, the data output by the ADCs is random and
should not be interpreted as valid data.
Data Mode
Once the device has been configured by programming the cor-
rect settings to the various control registers, the device may exit
Program Mode and enter Data Mode. This is done by program-
ming the DATA/
PGM
(CRA:0) bit to a 1 and MM (CRA:1) to
0. Once the device is in Data Mode, the 16-bit input data frame
is now interpreted as DAC data rather than a control frame.
This data is therefore loaded directly to the DAC register. In
Data Mode, as the entire input data frame contains DAC data,
the device relies on counting the number of input frame syncs
received at the SDIFS pin. When that number equals the device
count stored in the device count field of CRA, the device knows
that the present data frame being received is its own DAC up-
date data. When the device is in normal Data Mode (i.e., mixed
mode disabled), it must receive a hardware reset to reprogram
any of the control register settings. In a single AD73422 con-
figuration, each 16-bit data frame sent from the DSP to the
device is interpreted as DAC data but it is necessary to send two
DAC words per sample period in order to ensure DAC update.
Also as the device count setting defaults to 1, it must be set
to 2 (001b) to ensure correct update of both DACs on the
AD73422.
Mixed Program/Data Mode
This mode allows the user to send control words to the device
along with the DAC data. This permits adaptive control of the
device whereby control of the input/output gains can be effected
by interleaving control words along with the normal flow of
DAC data. The standard data frame remains 16 bits, but now
the MSB is used as a flag bit to indicate whether the remaining
15 bits of the frame represent DAC data or control information.
In the case of DAC data, the 15 bits are loaded with MSB
justification and LSB set to 0 to the DAC register. Mixed mode
is enabled by setting the MM bit (CRA:1) to 1 and the DATA/
PGM
bit (CRA:0) to 1. In the case where control setting changes
will be required during normal operation, this mode allows the
ability to load both control and data information with the slight
inconvenience of formatting the data. Note that the output
samples from the ADC will also have the MSB set to zero to
indicate it is a data word.
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