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参数资料
| 型号： | AD73422 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer(带DSP微计算机的双模拟前端) |
| 中文描述： | 双低功耗CMOS模拟前端（带DSP的微计算机的双模拟前端与DSP的微机） |
| 文件页数： | 4/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422 |
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REV. 0
–4–
AD73422–SPECIFICATIONS
Parameter
Test Conditions
Min
Typ
Max
Units
DSP SECTION
V
IH
V
IH
V
IL
V
OH
Hi-Level Input Voltage
1, 2
Hi-Level CLKIN Voltage
Lo-Level Input Voltage
1, 3
Hi-Level Output Voltage
1, 4, 5
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
I
OH
= –0.5 mA
@ VDD = min
I
OH
= –100
μ
A
6
@ VDD = min
I
OL
= 2 mA
@ VDD = max
V
IN
= VDD max
@ VDD = max
V
IN
= 0 V
@ VDD = max
V
IN
= VDD max
8
@ VDD = max
V
IN
= 0 V
8
@ VDD = 3.6
t
CK
= 19 ns
10
t
CK
= 25 ns
10
t
CK
= 30 ns
10
@ VDD = 3.6
T
AMB
= +25
°
C
t
CK
= 19 ns
10
t
CK
= 25 ns
10
t
CK
= 30 ns
10
@ V
IN
= 2.5 V
f
IN
= 1.0 MHz
T
AMB
= +25
°
C
@ V
IN
= 2.5 V
f
IN
= 1.0 MHz
T
AMB
= +25
°
C
2.0
2.2
V
V
V
0.8
2.4
V
V
DD
– 0.3
V
V
OL
Lo-Level Output Voltage
1, 4, 5
0.4
V
I
IH
Hi-Level Input Current
3
10
μ
A
I
IL
Lo-Level Input Current
3
10
μ
A
I
OZH
Three-State Leakage Current
7
10
μ
A
I
OZL
Three-State Leakage Current
7
10
μ
A
I
DD
Supply Current (Idle)
9
12
10
9
mA
mA
mA
I
DD
Supply Current (Dynamic)
11
54
43
37
mA
mA
mA
C
I
Input Pin Capacitance
3, 6, 12
8
12
pF
C
O
Output Pin Capacitance
6, 7, 12, 13
10
20
pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins:
RESET
,
BR
, DR0, DR1,
PWD
.
3
Input only pins: CLKIN,
RESET
, BR, DR0, DR1,
PWD
.
4
Output pins:
BG
,
PMS
,
DMS
,
BMS
,
IOMS
,
CMS
,
RD
,
WR
, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0,
BGH
.
5
Although specified for TTL outputs, all AD73422 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23,
PMS
,
DMS
,
BMS
,
IOMS
,
CMS
,
RD
,
WR
, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8
0 V on
BR
.
9
Idle refers to AD73422 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10
V
IN
= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11
I
DD
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
12
Applies to PBGA package type.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, f
DMCLK
= 16.384 MHz,
f
SAMP
= 64 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
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