参数资料
型号: AD73422
厂商: Analog Devices, Inc.
英文描述: Dual Low Power CMOS Analog Front End with DSP Microcomputer(带DSP微计算机的双模拟前端)
中文描述: 双低功耗CMOS模拟前端(带DSP的微计算机的双模拟前端与DSP的微机)
文件页数: 32/36页
文件大小: 396K
代理商: AD73422
REV. 0
AD73422
32
TFS
DT
SCLK
DR
RFS
DSP
SECTION
AD73422
AFE
SECTION
SDIFS
SDI
SCLK
SDO
SDOFS
FL0
FL1
ARESET
SE
Figure 22. AD73422 AFE to DSP Connection
Cascade Operation
Where it is required to configure extra analog I/O channels to
the existing two channels on the AD73422, it is possible to
cascade up to six more channels (using single channel AD73311
or dual channel AD73322 AFEs) by using the scheme described
in Figure 24. It is necessary, however, to ensure that the timing
of the SE and
ARESET
signals is synchronized at each device in
the cascade. A simple D-type flip-flop is sufficient to sync each
signal to the master clock AMCLK, as in Figure 23.
1/2
74HC74
CLK
D
Q
DSP
CONTROL
TO SE
AMCLK
SE SIGNAL
SYNCHRONIZED
TO AMCLK
DSP
CONTROL
TO
ARESET
AMCLK
ARESET
SIGNAL
SYNCHRONIZED
TO AMCLK
1/2
74HC74
CLK
D
Q
Figure 23. SE and
ARESET
Sync Circuit for Cascaded
Operation
Connection of a cascade of devices to a DSP, as shown in Fig-
ure 24, is no more complicated than connecting a single device.
Instead of connecting the SDO and SDOFS to the DSP’s Rx
port, these are now daisy-chained to the SDI and SDIFS of the
next device in the cascade. The SDO and SDOFS of the final
device in the cascade are connected to the DSP section’s Rx
port to complete the cascade. SE and
ARESET
on all devices
are fed from the signals that were synchronized with the AMCLK
using the circuit as described above. The SCLK from only one
device need be connected to the DSP section’s SCLK input(s)
as all devices will be running at the same SCLK frequency and
phase.
TFS
DT
DR
RFS
AFE
SECTION
SDIFS
SDI
SCLK
SDO
SDOFS
SCLK
DEVICE 1
AMCLK
SE
ARESET
ADDITIONAL
AD73322
CODEC
SDIFS
SDI
SCLK
SDO
SDOFS
DEVICE 2
AMCLK
SE
ARESET
74HC74
Q1
Q2
D1
D2
FL0
FL1
DSP
SECTION
Figure 24. Connection of an AD73322 Cascaded to
AD73422
Interfacing to the AFE’s Analog Inputs and Outputs
The AFE section of the AD73422 offers a flexible interface for
microphone pickups, line level signals or PSTN line interfaces.
This section will detail some of the configurations that can be
used with the input and output sections.
The AD73422 features both differential inputs and outputs on
each channel to provide optimal performance and avoid common-
mode noise. It is also possible to interface either inputs or out-
puts in single-ended mode. This section details the choice of
input and output configurations and also gives some tips toward
successful configuration of the analog interface sections.
CONTINUOUS
TIME
LOW-PASS
FILTER
V
REF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
AD73422
V
REF
+6/
15dB
PGA
REFERENCE
0/38dB
PGA
0.047 F
0.047 F
100
100
ANTIALIAS
FILTER
0.1 F
GAIN
1
Figure 25. Analog Input (DC-Coupled)
相关PDF资料
PDF描述
AD73422BB-40 Dual Low Power CMOS Analog Front End with DSP Microcomputer
AD73460BB-80 Six-Input Channel Analog Front End
AD73460 Six-Input Channel Analog Front End
AD73460BB-40 Six-Input Channel Analog Front End
AD7346B 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
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