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参数资料
| 型号： | AD73422 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer(带DSP微计算机的双模拟前端) |
| 中文描述： | 双低功耗CMOS模拟前端（带DSP的微计算机的双模拟前端与DSP的微机） |
| 文件页数： | 31/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422 |
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REV. 0
AD73422
–
31
–
The following pins are also used by the EZ-ICE:
BR
BG
RESET
GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the AD73422 in the target system. This causes the pro-
cessor to use its
ERESET
,
EBR
and
EBG
pins instead of the
RESET
,
BR
and
BG
pins. The
BG
output is three-stated. These
signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in length
with one end fixed to the EZ-ICE. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target
board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 21. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Figure 21. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1
×
0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as speci-
fied in the DSP’s data sheet. The performance of the EZ-ICE
may approach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction:
All memory strobe signals on the AD73422 (
RD
,
WR
,
PMS
,
DMS
,
BMS
,
CMS
and
IOMS
) used in your target
system must have 10 k
pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary be-
cause there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
EZ-ICE emulation ignores RESET and BR when single-
stepping.
EZ-ICE emulation ignores RESET and BR when in Emula-
tor Space (DSP halted).
EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
ANALOG FRONT END (AFE) INTERFACING
The AFE section of the AD73422 features two voiceband input/
output channels, each with 16-bit linear resolution. Connectiv-
ity to the AFE section from the DSP is uncommitted, thus
allowing the user the flexibility of connecting in the mode or
configuration of their choice. This section will detail several
configurations—with no extra AFE channels configured and
with two extra AFE channels configured (using an external
AD73322 dual AFE).
DSP SPORT to AFE Interfacing
The SCLK, SDO, SDOFS, SDI and SDIFS pins of SPORT2
must be connected to the Serial Clock, Receive Data, Receive
Data Frame Sync, Transmit Data and Transmit Data Frame
Sync pins respectively of either SPORT0 or SPORT1. The SE
pin may be controlled from a parallel output pin or flag pin such
as FL0-2 or, where SPORT2 power-down is not required, it can
be permanently strapped high using a suitable pull-up resistor.
The
ARESET
pin may be connected to the system hardware
reset structure or it may also be controlled using a dedicated
control line. In the event of tying it to the global system reset, it
is advisable to operate the device in mixed mode, which allows a
software reset, otherwise there is no convenient way of resetting
the AFE section.
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