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| 型号： | AD7712ARZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SGNL CONDTNR 24SOIC |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 1.03k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极；1 个差分，单极；1 个差分，双极 |
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REV. F
–14–
AD7712
Input Sample Rate
The modulator sample frequency for the device remains at
fCLK IN/512 (19.5 kHz @ fCLK IN = 10 MHz) regardless of the
selected gain. However, gains greater than
1 are achieved by
a combination of multiple input samples per modulator cycle
and scaling the ratio of reference capacitor to input capacitor.
As a result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The
effective input impedance is 1/C
fS where C is the input
sampling capacitance and fS is the input sample rate.
Table III. Input Sampling Frequency vs. Gain
Gain
Input Sampling Frequency (fS)
1fCLK IN/256 (39 kHz @ fCLK IN = 10 MHz)
22
fCLK IN/256 (78 kHz @ fCLK IN = 10 MHz)
44
fCLK IN/256 (156 kHz @ fCLK IN = 10 MHz)
88
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
16
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
32
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
64
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
128
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
DIGITAL FILTERING
The AD7712’s digital filter behaves like a similar analog filter,
with a few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal
is within limits. To alleviate this problem, the AD7712 has
overrange headroom built into the sigma-delta modulator and
digital filter, which allows overrange excursions of 5% above
the analog input range. If noise signals are larger than this,
consideration should be given to analog input filtering, or to
reducing the input channel voltage so that its full scale is half
that of the analog input channel full scale. This will provide
an overrange capability greater than 100% at the expense of
reducing the dynamic range by 1 bit (50%).
Filter Characteristics
The cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At
the maximum clock frequency of 10 MHz, the minimum
cutoff frequency of the filter is 2.58 Hz while the maximum
programmable cutoff frequency is 269 Hz.
Figure 6 shows the filter frequency response for a cutoff
frequency of 2.62 Hz, which corresponds to a first filter notch
frequency of 10 Hz. This is a (sinx/x)
3 response (also called
sinc
3), that provides >100 dB of 50 Hz and 60 Hz rejection.
Programming a different cutoff frequency via FS0–FS11 does
not alter the profile of the filter response; it changes the fre-
quency of the notches as outlined in the Control Register
section.
0
–240
–180
–220
10
–200
0
–120
–160
–140
–100
–80
–60
–20
–40
60
50
40
30
20
FREQUENCY – Hz
GAIN
–
dB
Figure 6. Frequency Response of AD7712 Filter
Since the AD7712 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency, and the settling time of
the filter to a full-scale step input is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from the
second channel is accessed.
Post Filtering
The on-chip modulator provides samples at a 19.5 kHz output
rate. The on-chip digital filter decimates these samples to pro-
vide data at an output rate that corresponds to the programmed
first notch frequency of the filter. Since the output data rate
exceeds the Nyquist criterion, the output rate for a given band-
width will satisfy most application requirements. However, there
may be some applications that require a higher data rate for a
given bandwidth and noise performance. Applications that need
this higher data rate will require some post filtering following
the digital filter of the AD7712.
For example, if the required bandwidth is 7.86 Hz but the
required update rate is 100 Hz, the data can be taken from the
AD7712 at the 100 Hz rate giving a –3 dB bandwidth of
26.2 Hz. Post filtering can be applied to this to reduce the
bandwidth and output noise, to the 7.86 Hz bandwidth level,
while maintaining an output rate of 100 Hz.
Post filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 2.62 Hz,
the noise in the resultant passband can be reduced. A reduction
in bandwidth by a factor of 2 results in a
√2 reduction in the
output rms noise. This additional filtering will result in a longer
settling time.
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相关代理商/技术参数 |
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|---|---|
| AD7712ARZ-REEL7 | 功能描述:IC ADC 24BIT SGNL CONDTNR 24SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7712EB | 制造商:AD 制造商全称:Analog Devices 功能描述:LC 2 MOS Signal Conditioning ADC(229.08 k) |
| AD7712SQ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:24 BIT SIGMA DELTA ADC IC - Bulk |
| AD7713 | 制造商:AD 制造商全称:Analog Devices 功能描述:LC2MOS Loop-Powered Signal Conditioning ADC |
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