参数资料
型号: AD9148BBPZRL
厂商: Analog Devices Inc
文件页数: 23/72页
文件大小: 0K
描述: IC DAC 16BIT SPI/SRL 196BGA
标准包装: 1,500
系列: TxDAC+®
设置时间: 20ns
位数: 16
数据接口: 串行,SPI?
转换器数目: 4
电压电源: 单电源
功率耗散(最大): 2.67W
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 196-LFBGA 裸露焊盘
供应商设备封装: 196-BGA
包装: 带卷 (TR)
输出数目和类型: 4 电流,单极
采样率(每秒): 1G
Data Sheet
AD9148
Rev. B | Page 3 of 72
REVISION HISTORY
1/12—Rev. A to Rev. B
Change to Chip ID Default Value, Table 12.................................25
Change to Chip ID Readback Value, Table 13.............................32
Changed 0x02 to 0x0A ...................................................................65
9/11—Rev. 0 to Rev. A
Changes to General Description Section .......................................1
Deleted Input High Voltage, VIA or VIB Parameter, Table 2, Input
Low Voltage, VIA or VIB Parameter, Table 2, and
Note 2, Table 2; Renumbered Sequentially ....................................6
Added Input Voltage Range, VIA or VIB Parameter, Table 2.........6
Changes to Table 10 ........................................................................13
Changes to Figure 41 and Figure 42 .............................................23
Changes to 0x1E Addr, Table 12....................................................24
Deleted 0x74 Row, Table 12 ...........................................................26
Changes to PLL Control 2, Table 13 .............................................29
Changes to HB3 Control, 1E, Bit 7 Row, Table 13 ......................32
Deleted LVDS Pad Ctrl Row, Table 13..........................................38
Deleted Frame Input Levels Section and Table 15......................41
Added Recommended Frame Input Bias Circuitry Section and
Figure 45; Renumbered Sequentially............................................41
Changes to Timing Optimization Section...................................48
Added Table 15................................................................................48
Changes to Filter Implementation Section ..................................50
Changes to Figure 74 ......................................................................57
Deleted Test Access Port Section, Table 27, Figure 92, and
Table 28.............................................................................................68
Changes to Start-Up Sequence Section........................................68
Deleted Figure 93 ............................................................................69
Deleted Table 29 ..............................................................................70
6/10—Revision 0: Initial Version
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