参数资料
| 型号： | AD9148BBPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/72页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SPI/SRL 196BGA |
| 标准包装： | 1,500 |
| 系列： | TxDAC+® |
| 设置时间： | 20ns |
| 位数： | 16 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 2.67W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA 裸露焊盘 |
| 供应商设备封装： | 196-BGA |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 1G |
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AD9148
Data Sheet
Rev. B | Page 42 of 72
FIFO OPERATION
DAC1
AND
DAC2
32
32 BITS
÷INT
DCIA
DCIB
DACCLK
DATA
PORT A
DATA
PORT B
DATA
PATHS
DATA
ASSEMBLER
INPUT
LATCH
DATA
ASSEMBLER
INPUT
LATCH
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
32
DAC3
AND
DAC4
32
DATA
PATHS
32
WRITE PTR
RESET
WRITE PTR
RESET
READ
PTR
RESET
SYNC
LOGIC
FIFO RATE/
DATA RATE
FI
F
O
A
O
F
S
[2:
0]
FI
F
O
B
OF
S
[2
:0
]
32 BITS
FRAMEB
FRAMEA
LOGIC
RE
AD
P
O
IN
T
E
R
A
R
E
AD
P
O
INT
E
R
B
32
INTERFACE
MODE
ONE
DCI
WRITE PTR B
WRITE PTR A
08
91
0-
049
Figure 50. Block Diagram of FIFO
The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one
per dual DAC) designed to relax the timing relationship between
the data arriving at the DAC input ports and the internal DAC
data rate clock. The FIFOs can also be used to provide an adjustable
pipeline delay between the DCIx clocks and the DACCLK allowing
realignment of data input in a multichip system. This significantly
increases the timing budget of the interface.
Figure 50 shows the block diagram of the datapath through the
FIFO. The data is latched into the device, is formatted, and is then
written into the FIFO register determined by the FIFO write
pointer. The value of the write pointer is incremented every time a
new word is loaded into the FIFO. Meanwhile, data is read from
the FIFO register determined by the read pointer and fed into
the digital datapath. The value of the read pointer is updated
every time data is read into the datapath from the FIFO. This
happens at the data rate, that is, the DACCLK rate divided by
the interpolation ratio. The difference between the write and
read pointers represents the FIFO pipeline delay and is
important to take into account when understanding the overall
pipeline delay of the AD9148.
In single-port and byte interface modes, the incoming digital data is
sampled at twice the data rate (DCIA). The data is then assembled
based on the interface mode. At the output of the data assembler
block, the data samples for DAC 1 and DAC 2 are written to FIFO A
and the data samples for DAC 3 and DAC 4 are written to FIFO B
at the data rate.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. An overflow or empty
condition of the FIFO is the same as the write pointer and the
read pointer being equal. When both pointers are equal, an attempt
is made to read and write a single FIFO register simultaneously.
This simultaneous register access leads to unreliable data transfer
through the FIFO and must be avoided.
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| AD9148BPCZRL | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148-EBZ | 功能描述:BOARD EVALUATION FOR AD9148 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148-M5372-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5372 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5375 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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