参数资料
| 型号： | AD9148BBPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 60/72页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SPI/SRL 196BGA |
| 标准包装： | 1,500 |
| 系列： | TxDAC+® |
| 设置时间： | 20ns |
| 位数： | 16 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 2.67W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA 裸露焊盘 |
| 供应商设备封装： | 196-BGA |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 1G |
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Data Sheet
AD9148
Rev. B | Page 63 of 72
DEVICE POWER DISSIPATION
The AD9148 has four supply rails: AVDD33, IOVDD, DVDD18,
and CVDD18.
The AVDD33 supply powers the DAC core circuitry. The power
dissipation of the AVDD33 supply rail is independent of the digital
operating mode and sample rate. The current drawn from the
AVDD33 supply rail is typically 98 mA (320 mW) when the
full-scale current of the four main DACs (DAC 1, DAC 2, DAC 3,
and DAC 4) is set to the nominal value of 20 mA. Changing the
full-scale current directly impacts the supply current drawn from
the AVDD33 rail. For example, if the full-scale current of the
four main DACs is changed to 10 mA, the AVDD33 supply
current drops by 40 mA to 58 mA.
The IOVDD voltage supplies the serial port I/O pins (SCLK,
SDIO, SDO, CSB, TCK, TDI, TDO, TMS), the RESET pin, and
the IRQ pin. The voltage applied to the IOVDD pin can range
from 1.8 V to 3.3 V. The current drawn by the IOVDD supply
pin is typically 1 mA.
The DVDD18 supply powers all of the digital signal processing
blocks of the device. The power consumption from this supply
is a function of which digital blocks are enabled and the frequency
at which the device is operating.
The CVDD18 supply powers the clock receiver and clock
distribution circuitry. The power consumption from this
supply varies directly with the operating frequency of the
device. CVDD18 also powers the PLL. The power dissipation
of the PLL is typically 80 mW.
under a variety of operating conditions. All of the graphs are
taken with data being supplied to all four DACs. The power
consumption of the device does not vary significantly with
changes in the coarse modulation mode selected or analog
output frequency. Graphs of the total power dissipation are
shown along with the power dissipation of the DVDD18 and
CVDD18 supplies.
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
fDATA (MSPS)
PO
W
ER
D
ISSI
PA
TION
(
W)
1×
2×
4×
8×
08910-
082
Figure 84. Total Power Dissipation vs. fDATA with Coarse Modulation, PLL, and
Inverse Sinc Filter Disabled
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
fDATA (MSPS)
PO
W
ER
D
ISSI
PA
TION
(
W)
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
08910-
083
1×
2×
4×
8×
Figure 85. Total Power Dissipation vs. fDATA with Fine Modulation, PLL, and
Inverse Sinc Filter Disabled
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
fDATA (MSPS)
PO
W
ER
D
ISSI
PA
TION
(
W)
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
08910-
084
1×
2×
4×
8×
Figure 86. DVDD18 Power Dissipation vs. fDATA with Coarse Modulation, PLL,
and Inverse Sinc Filter Disabled
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
fDATA (MSPS)
PO
W
ER
D
ISSI
PA
TION
(
W)
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
08910-
085
1×
2×
4×
8×
Figure 87. DVDD18 Power Dissipation vs. fDATA with Fine Modulation, PLL,
and Inverse Sinc Filter Disabled
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