参数资料
| 型号： | AD9148BBPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 42/72页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SPI/SRL 196BGA |
| 标准包装： | 1,500 |
| 系列： | TxDAC+® |
| 设置时间： | 20ns |
| 位数： | 16 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 2.67W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA 裸露焊盘 |
| 供应商设备封装： | 196-BGA |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 1G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页当前第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
Data Sheet
AD9148
Rev. B | Page 47 of 72
SAMPLE RATE CLOCK
FPGA
LOW SKEW
CLOCK DRIVER
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
CLK
FRAME
DCI
OUT1
OUT2
SYNC CLOCK
REFCLK/SYNC
CLK
FRAME
DCI
REFCLK/SYNC
MATCHED
LENGTH TRACES
08910-
054
Figure 55. Typical Circuit Diagram for Synchronizing Devices to a System Clock
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock to CLK, a
separate REFCLK/SYNC input signal is required for synchronization.
To synchronize devices, the CLK signals and the REFCLK/SYNC
signals must be distributed with low skew to all of the devices
being synchronized. This configuration is shown below in
Data Rate Mode Synchronization
The following procedure outlines the steps required to synchronize
multiple devices in data rate mode. The procedure assumes that
the CLK and REFCLK/SYNC signals are applied to all of the
devices. Each individual device must follow the procedure.
The procedure for data rate synchronization when directly
sourcing the DAC sampling clock follows:
1. Configure for data rate, periodic synchronization by
writing 0xC0 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
2. Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
3. Reset the FIFO by strobing the FRAME signal for at least the
time interval needed to load complete data to the four DACs
Resetting the FIFO ensures that the correct data is being
read from the FIFO of each of the devices simultaneously.
This completes the synchronization procedure, and at this
stage, all devices should be synchronized.
To ensure that each of the DACs are updated with the correct data
on the same DACCLK edge, two timing relationships must be
met on each DAC. DCI (and data) must meet the setup and hold
times with respect to the rising edge of CLK, and REFCLK/SYNC
must also meet the setup and hold time with respect to the
rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dual-
port mode and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within tSKEW + tOUTDLY nanoseconds of each other. A timing
diagram that illustrates the timing requirements of the input
signals is shown in Figure 56.
CLK(1)
CLK(2)
SYNC(2)
FRAME(2)
DCI(2)
tSKEW
tH_DCI
tSU_DCI
tH_SYNC
tSU_SYNC
08910-
055
Figure 56. Synchronization Signal Timing Requirements in Data Rate Mode,
2× Interpolation
Figure 56 shows the synchronization signal timing with 2×
interpolation, so that fDCI = × fCLK. The REFCLK/SYNC input
is shown equal to the DCI rate. The maximum frequency at which
the device can be resynchronized in data rate mode can be
expressed as
N
DATA
SYNC
f
2
=
for any positive integer, N.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9200ARS | IC ADC CMOS 10BIT 20MSPS 28-SSOP |
| AD9201ARS | IC ADC CMOS 10BIT DUAL 28-SSOP |
| AD9203ARU | IC ADC 10BIT 40MSPS 3V 28-TSSOP |
| AD9204BCPZRL7-80 | IC ADC 10BIT 80MSPS 64LFCSP |
| AD9211BCPZ-200 | IC ADC 10-BIT 200MSPS 56-LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9148BPCZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148BPCZRL | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148-EBZ | 功能描述:BOARD EVALUATION FOR AD9148 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148-M5372-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5372 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5375 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
发布紧急采购，3分钟左右您将得到回复。