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| 型号： | AD9258BCPZ-125 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS DL 64LFCSP |
| 设计资源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 788mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个差分，单极 |
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AD9258
Rev. A | Page 27 of 44
Common-Mode Voltage Servo
In applications where there may be a voltage loss between the VCM
output of the AD9258 and the analog inputs, the common-mode
voltage servo can be enabled. When the inputs are ac-coupled and
a resistance of >100 Ω is placed between the VCM output and the
analog inputs, a significant voltage drop can occur and the
common-mode voltage servo should be enabled. Setting Bit 0 in
Register 0x0F to a logic high enables the VCM servo mode. In
this mode, the AD9258 monitors the common-mode input level
at the analog inputs and adjusts the VCM output level to keep
the common-mode input voltage at an optimal level. If both
channels are operational, Channel A is monitored. However,
if Channel A is in power-down or standby mode, then the
Channel B input is monitored.
Dither
The AD9258 has an optional dither mode that can be selected
for one or both channels. Dithering is the act of injecting a known
but random amount of white noise, commonly referred to as
dither, into the input of the ADC. Dithering has the effect of
improving the local linearity at various points along the ADC
transfer function. Dithering can significantly improve the SFDR
when quantizing small-signal inputs, typically when the input
level is below 6 dBFS.
As shown in Figure 65, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is
enabled, the dither DAC is driven by a pseudorandom number
generator (PN gen). In the AD9258, the dither DAC is precisely
calibrated to result in only a very small degradation in SNR and
the SINAD. The typical SNR and SINAD degradation values,
with dithering enabled, are only 1 dB and 0.8 dB, respectively.
ADC CORE
DITHER
DAC
PN GEN
DITHER ENABLE
AD9258
VIN
DOUT
08
12
4-
05
8
Figure 65. Dither Block Diagram
Large-Signal FFT
In most cases, dithering does not improve SFDR for large-signal
inputs close to full-scale, for example with a 1 dBFS input. For
large-signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve. However,
even for such large-signal inputs, dithering may be useful for
certain applications because it makes the noise floor whiter.
As is common in pipeline ADCs, the AD9258 contains small
DNL errors caused by random component mis-matches that
produce spurs or tones that make the noise floor somewhat
randomly colored part-to-part. Although these tones are
typically at very low levels and do not limit SFDR when the
ADC is quantizing large-signal inputs, dithering converts these
tones to noise and produces a whiter noise floor.
Small-Signal FFT
For small-signal inputs, the front-end sampling circuit typically
contributes very little distortion, and, therefore, the SFDR is
likely to be limited by tones caused by DNL errors due to random
component mismatches. Therefore, for small-signal inputs (typi-
cally, those below 6 dBFS), dithering can significantly improve
SFDR by converting these DNL tones to white noise.
Static Linearity
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-to-
peak INL.
In receiver applications, utilizing dither helps to reduce DNL
errors that cause small-signal gain errors. Often this issue is
overcome by setting the input noise 5 dB to 10 dB above the
converter noise. By utilizing dither within the converter to correct
the DNL errors, the input noise requirement can be reduced.
Differential Input Configurations
Optimum performance is achieved while driving the AD9258
in a differential input configuration. For baseband applications,
provide excellent performance and a flexible interface to the
ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9258 (see Figure 66), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
VIN
76.8
120
0.1F
200
200
90
AVDD
33
33
15
15
5pF
15pF
AD9258
VIN–
VIN+
VCM
08
12
4-
03
5
ADA4938-2
Figure 66. Differential Input Configuration Using the ADA4938-2
For baseband applications in which SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 67. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
2V p-p
49.9
0.1F
R1
C1
08
12
4-
0
36
AD9258
VIN+
VIN–
VCM
C2
R2
C2
Figure 67. Differential Transformer-Coupled Configuration
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相关代理商/技术参数 |
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| AD9258BCPZ-1251 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| AD9258BCPZ-80 | 功能描述:模数转换器 - ADC Dual 14 bit 80 high SNR ADC RoHS:否 制造商:Analog Devices 通道数量: 结构: 转换速率: 分辨率: 输入类型: 信噪比: 接口类型: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| AD9258BCPZ-801 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| AD9258BCPZRL7-105 | 功能描述:模数转换器 - ADC Dual 14 bit 105 highSNR ADC RoHS:否 制造商:Analog Devices 通道数量: 结构: 转换速率: 分辨率: 输入类型: 信噪比: 接口类型: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| AD9258BCPZRL7-1051 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
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