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参数资料
| 型号： | AD9287BCPZRL7-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT QUAD 100MSPS 48LFCSP |
| 产品变化通告： | Product Discontinuation 12/Mar/2010 |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 100M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 562mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 标准包装 |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极 |
| 配用： | AD9287-100EBZ-ND - BOARD EVALUATION AD9287 |
| 其它名称： | AD9287BCPZRL7-100DKR |
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AD9287
Data Sheet
Rev. E | Page 20 of 52
For best dynamic performance, the source impedances driving
VIN + x and VIN x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9287, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9287 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the AD8332
differential driver to drive the AD9287 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 41) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 38 and Figure 39), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9287.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
2V p-p
R
1CDIFF
C
1CDIFF IS OPTIONAL
49.9
0.1μF
1k
AGND
AVDD
ADT1-1WT
1:1 Z RATIO
VIN – x
ADC
AD9287
VIN + x
C
05
96
6-
0
08
Figure 38. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9287
2V p-p
2.2pF
1k
0.1μF
1k
AVDD
ADT1-1WT
1:1 Z RATIO
16nH
0.1μF
16nH
33
499
65
VIN + x
VIN – x
059
66-
04
7
Figure 39. Differential Transformer-Coupled Configuration
for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the ADC’s VIN + x pin while the
VIN x pin is terminated. Figure 40 details a typical single-
ended input configuration.
2V p-p
R
49.9
0.1F
AVDD
1k 25
1k
AVDD
VIN – x
ADC
AD9287
VIN + x
C
05
96
6-
0
9
1CDIFF
1CDIFF IS OPTIONAL
Figure 40. Single-Ended Input Configuration
AD8332
1k
187
0.1μF
1V p-p
0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF
274
VIN – x
ADC
AD9287
VIN + x
05
96
6-
0
07
LPF
+
68pF
33
AVDD
680nH
10k
Figure 41. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
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