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参数资料
| 型号： | AD9287BCPZRL7-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT QUAD 100MSPS 48LFCSP |
| 产品变化通告： | Product Discontinuation 12/Mar/2010 |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 100M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 562mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 标准包装 |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极 |
| 配用： | AD9287-100EBZ-ND - BOARD EVALUATION AD9287 |
| 其它名称： | AD9287BCPZRL7-100DKR |
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AD9287
Data Sheet
Rev. E | Page 30 of 52
05
96
6-
0
90
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V
)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
030
20
10
40
50
60
70
80
90
100
Figure 57. SDIO Pin Loading
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
For users who wish to operate the ADC without using the SPI,
remove any connections from the CSB, SCLK/DTP, and SDIO/
ODM pins. By disconnecting these pins from the control bus, the
ADC can function in its most basic operation. Each of these pins
has an internal termination that floats to its respective level.
DON’T CARE
SDIO
SCLK
CSB
tS
tDH
tHI
tCLK
tLO
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
0
596
6-
01
2
Figure 58. Serial Timing Details
Table 15. Serial Timing Definitions
Parameter
Timing (Minimum, ns)
Description
tDS
5
Setup time between the data and the rising edge of SCLK
tDH
2
Hold time between the data and the rising edge of SCLK
tCLK
40
Period of the clock
tS
5
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHI
16
Minimum period that SCLK should be in a logic high state
tLO
16
Minimum period that SCLK should be in a logic low state
tEN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 58)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 58)
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