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| 型号： | AD9287BCPZRL7-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT QUAD 100MSPS 48LFCSP |
| 产品变化通告： | Product Discontinuation 12/Mar/2010 |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 100M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 562mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 标准包装 |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极 |
| 配用： | AD9287-100EBZ-ND - BOARD EVALUATION AD9287 |
| 其它名称： | AD9287BCPZRL7-100DKR |
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AD9287
Data Sheet
Rev. E | Page 26 of 52
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to refine
system timing margins if required. The default DCO+ and DCO
timing, as shown in Figure 2, is 90° relative to the output data edge.
A 10-, 12-, or 14-bit serial stream can also be initiated from the
SPI. This allows the user to implement and test compatibility with
higher resolution systems. However, when using the 12-bit option,
the data stream stuffs four 0s at the end of the 12-bit serial data
(see Figure 3).
When the SPI is used, all of the data outputs can also be
inverted from their nominal state. This is not to be confused
with inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is first in the data output
serial stream. However, this can be inverted so that the LSB is
first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various ways,
depending on the test pattern chosen. Note that some patterns do
not adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in the 0x19, 0x1A,
0x1B, and 0x1C register addresses. All test mode options except
PN sequence short and PN sequence long can support 8- to 14-bit
word lengths in order to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9287 inverts the bit stream with relation to the ITU standard.
Table 10. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short
0x0df
0xbf, 0x93, 0x53
PN Sequence Long
0x029b80
0xf5, 0x91, 0xfd
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require
SPI mode operation. This pin can enable a low power, reduced
signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
device power-up. This option should only be used when the
digital output trace lengths are less than 2 inches from the LVDS
receiver. When this option is used, the FCO, DCO, and outputs
function normally, but the LVDS signal swing of all channels is
reduced from 350 mV p-p to 200 mV p-p, allowing the user to
further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low.
In this case, the device pin can be left open, and the 30 k internal
pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.
If applications require this pin to be driven from a 3.3 V logic level,
insert a 1 k resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Selected ODM
ODM Voltage
Resulting
Output Standard
Resulting
FCO and DCO
Normal
Operation
10 k to AGND
ANSI-644
(default)
ANSI-644
(default)
ODM
AVDD
Low power,
reduced
signal option
Low power,
reduced
signal option
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