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参数资料
| 型号： | AD9287BCPZRL7-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT QUAD 100MSPS 48LFCSP |
| 产品变化通告： | Product Discontinuation 12/Mar/2010 |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 100M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 562mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 标准包装 |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极 |
| 配用： | AD9287-100EBZ-ND - BOARD EVALUATION AD9287 |
| 其它名称： | AD9287BCPZRL7-100DKR |
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AD9287
Data Sheet
Rev. E | Page 22 of 52
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 47).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9287.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs at www.analog.com.
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
NR
(
d
B)
05966-
038
Figure 47. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 48, the power dissipated by the AD9287 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
0
120
ENCODE (MSPS)
CURRE
NT
(
mA)
PO
W
ER
(m
W
)
300
250
200
150
100
50
300
600
550
500
450
400
350
20
40
60
80
100
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
05966-
069
Figure 48. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 100 MSPS
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相关代理商/技术参数 |
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|---|---|
| AD9288 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 40/80/100 MSPS Dual A/D Converter |
| AD9288/PCB | 制造商:Analog Devices 功能描述:8 BIT 40/80/100 MSPS DUAL ADC EVAL BOARD - Bulk |
| AD9288BST-100 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 100Msps 8-bit Parallel 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 8-BIT ADC |
| AD9288BST-100 | 制造商:Analog Devices 功能描述:A/D CONVERTER (A-D) IC |
| AD9288BST-40 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 40Msps 8-bit Parallel 48-Pin LQFP 制造商:Analog Devices 功能描述:AD CONVERTOR ((NW)) |
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