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参数资料
| 型号： | AD9287BCPZRL7-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT QUAD 100MSPS 48LFCSP |
| 产品变化通告： | Product Discontinuation 12/Mar/2010 |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 100M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 562mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 标准包装 |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极 |
| 配用： | AD9287-100EBZ-ND - BOARD EVALUATION AD9287 |
| 其它名称： | AD9287BCPZRL7-100DKR |
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AD9287
Data Sheet
Rev. E | Page 32 of 52
Table 16. Memory Map Register
Addr.
(Hex)
Register Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00
chip_port_config
0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0
0x18
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
01
chip_id
8-bit Chip ID Bits [7:0]
(AD9287 = 0x05), (default)
0x05
Default is unique
chip ID, different
for each device.
This is a read-
only register.
02
chip_grade
X
Child ID [6:4]
(identify device variants of Chip ID)
011 = 100 MSPS
X
Read
only
Child ID used to
differentiate
graded devices.
Device Index and Transfer Registers
05
device_index_A
X
Clock
Channel
DCO
1 = on
0 = off
(default)
Clock
Channel
FCO
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
FF
device_update
X
SW
transfer
1 = on
0 = off
(default)
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08
modes
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
0x00
Determines
various generic
modes of chip
operation.
09
clock
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01
Turns the
internal duty
cycle stabilizer
on and off.
0D
test_io
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset
PN long
gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see Table 9 in the
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
0x00
When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.
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