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| 型号： | AD9516-1/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/80页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9516-1 |
| 产品培训模块： | Active Filter Design Tools |
| 设计资源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-1 BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-1 |
| 主要属性： | 2 输入，14 输出，2.5GHz VCO |
| 次要属性： | CMOS、LVDS、LVPECL 输出逻辑，ADIsimCLK&trade 图形用户界面 |
| 已供物品： | 板，线缆，电源 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 相关产品： | AD9516-1BCPZ-REEL7-ND - IC CLOCK GEN 2.5GHZ VCO 64-LFCSP AD9516-1BCPZ-ND - IC CLOCK GEN 2.5GHZ VCO 64-LFCSP |
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Data Sheet
AD9516-1
Rev. C | Page 39 of 80
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
R
E
NC
E
HOLD
0
1
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
06
420
-07
0
Figure 54. Reference and VCO Status Monitors
VCO Calibration
The AD9516 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be present.
During the first initialization after a power-up or a reset of the
AD9516, a VCO calibration sequence is initiated by setting
Register 0x018[0] = 1b. This can be done as part of the initial
setup, before executing update registers (Register 0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting Register 0x018[0] = 0b, executing an update
registers operation, setting Register 0x018[0] = 1b, and executing
another update registers operation. A readback bit, Bit 6 in
Register 0x01F, indicates when a VCO calibration is finished
by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
Program the PLL registers to the proper values for the PLL
loop. Note that that automatic holdover mode must be
disabled, and the VCO divider must not be set to “Static.”
Ensure that the input reference signal is present.
For the initial setting of the registers after a power-up or reset,
initiate VCO calibration by setting Register 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set
Register 0x018[0] = 0b, update registers; and then set
Register 0x018[0] = 1b, update registers.
A SYNC operation is initiated internally, causing the
outputs to go to a static state determined by normal SYNC
function operation.
VCO calibrates to the desired setting for the requested
VCO frequency.
Internally, the SYNC signal is released, allowing outputs to
continue clocking.
PLL loop is closed.
PLL locks.
A sync is executed during the VCO calibration; therefore, the
outputs of the AD9516 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 54
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 29. Example Time to Complete a VCO Calibration
with Different fREFIN Frequencies
fREFIN (MHz)
R Divider
PFD
Time to Calibrate VCO
100
1
100 MHz
88 μs
10
1 MHz
8.8 ms
10
100
100 kHz
88 ms
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相关代理商/技术参数 |
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| AD9516-1XCPZ | 制造商:Analog Devices 功能描述:14-CHANNEL CLOCK GENERATOR WITH INTEGRATED 2.8 GHZ VCO - Bulk |
| AD9516-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9516-2/PCBZ | 功能描述:BOARD EVAL FOR AD9516-2 2.2GHZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9516-2BCPZ | 功能描述:IC CLOCK PLL/VCO 2.2GHZ 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9516-2BCPZ-REEL7 | 功能描述:IC CLOCK PLL/VCO 2.2GHZ 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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