参数资料
| 型号： | AD9942BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR SGNL 14B 100CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，14 位 |
| 应用： | 数码相机 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（9x9） |
| 包装： | 带卷 (TR) |
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AD9942
Rev. A | Page 19 of 36
CHANNEL A AND CHANNEL B PRECISION TIMING
HIGH SPEED TIMING GENERATION
The AD9942 generates flexible, high speed timing signals using
the Precision Timing core for both channels. This core is the
foundation for generating the timing used for both the CCD
and the AFE, the reset gate RG_X, the horizontal drivers H1X
to H4X, and the SHP/SHD sample clocks. A unique architecture
makes it routine for the system designer to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE correlated double sampling.
TIMING RESOLUTION
The Precision Timing core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 48 steps or edge
positions. Therefore, the edge resolution of the Precision Timing
core is (tCLI/48). For more information on using the CLI input,
see the Applications Information section.
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 17 shows how the high speed clocks, RG_X, H1X to
H4X, SHP, and SHD, are generated. The RG_X pulse has
programmable rising and falling edges and can be inverted
using the polarity control. The horizontal clock, H1, has
programmable rising and falling edges and polarity control.
The H2 clock is always the inverse of the H1 clock. Table 17 sum-
marizes the high speed timing registers and their parameters.
Each edge location setting is six bits wide, but only 48 valid edge
locations are available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing
12 edge locations. Table 18 shows the correct register values for
the corresponding edge locations.
05
24
0-
0
19
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI_X INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
tCLIDLY = 6ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
CLI_X
tCLIDLY
POSITION
Figure 16. High Speed Clock Resolution from CLI
05
24
0
-02
0
H1X/H3X
H2X/H4X
CCD SIGNAL
RG_X
12
3
4
56
PROGRAMMABLE CLOCK POSITIONS:
1RG_X RISING EDGE.
2RG_X FALLING EDGE.
3SHP SAMPLE LOCATION.
4SHD SAMPLE LOCATION.
5H1X/H3X RISING EDGE POSITION.
6H1X/H3X FALLING EDGE POSITION (H2X/H4X ARE INVERSE OF H1X/H3X).
Figure 17. High Speed Clock Programmable Locations
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