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参数资料
型号： AD9942BBCZRL
厂商： Analog Devices Inc
文件页数： 9/36页
文件大小： 0K
描述： IC PROCESSOR SGNL 14B 100CSPBGA
标准包装： 2,000
类型： CCD 信号处理器，14 位
应用： 数码相机
安装类型： 表面贴装
封装/外壳： 100-LFBGA，CSPBGA
供应商设备封装： 100-CSBGA（9x9）
包装： 带卷 (TR)
AD9942
Rev. A | Page 17 of 36
Table 11. CHN_A and CHN_B CLPOB Register Map
Address
Data Bit Content
Default (Hex)
Name
Description (the CLPOBSCP0 Always Starts at Line 0)
20
[3:0]
F
CLPOBPOL
Start polarities for CLPOB Sequences 0, 1, 2, and 3.
21
[23:0]
FFFFFF
CLPOBTOG_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
22
[23:0]
FFFFFF
CLPOBTOG_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
23
[23:0]
FFFFFF
CLPOBTOG_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
24
[23:0]
FFFFFF
CLPOBTOG_3
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
25
[7:0]
00
CLPOBSPTR
CLPOB sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
26
[11:0]
FFF
CLPOBSCP1
CLPOB sequence—Change Position 1.
27
[11:0]
FFF
CLPOBSCP2
CLPOB sequence—Change Position 2.
28
[11:0]
FFF
CLPOBSCP3
CLPOB sequence—Change Position 3.
Table 12. PBLK Register Map
Address
Data Bit Content
Default (Hex)
Name
Description (the PBLKSCP0 Always Starts at Line 0)
30
[3:0]
F
PBLKPOL
Start polarities for PBLK Sequences 0, 1, 2, and 3.
31
[23:0]
FFFFFF
PBLKTOG_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
32
[23:0]
FFFFFF
PBLKTOG_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
33
[23:0]
FFFFFF
PBLKTOG_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
34
[23:0]
FFFFFF
PBLKTOG_3
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
35
[7:0]
00
PBLKSPTR
PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
36
[11:0]
FFF
PBLKSCP1
PBLK sequence—Change Position 1.
37
[11:0]
FFF
PBLKSCP2
PBLK sequence—Change Position 2.
38
[11:0]
FFF
PBLKSCP3
PBLK sequence—Change Position 3.
Table 13. HBLK Register Map
Address
Data Bit Content
Default (Hex)
Name
Description (the HBLKSCP0 Always Starts at Line 0)
40
[0]
0
TESTMODE
Test mode. Always set = 0 if accessed.
41
[0]
0
TESTMODE
Test mode. Always set = 0 if accessed.
42
[0]
1
TESTMODE
Test mode. Always set = 1 if accessed.
43
[3:0]
F
HBLKMASK
HBLK internal masking polarity. 0 = mask H1 low; 1 = mask H1 high.
44
[23:0]
FFFFFF
HBLKTOG12_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
45
[23:0]
FFFFFF
HBLKTOG34_0
Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
46
[23:0]
FFFFFF
HBLKTOG56_0
Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
47
[23:0]
FFFFFF
HBLKTOG12_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
48
[23:0]
FFFFFF
HBLKTOG34_1
Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
49
[23:0]
FFFFFF
HBLKTOG56_1
Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4A
[23:0]
FFFFFF
HBLKTOG12_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4B
[23:0]
FFFFFF
HBLKTOG34_2
Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4C
[23:0]
FFFFFF
HBLKTOG56_2
Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4D
[23:0]
FFFFFF
HBLKTOG12_3
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4E
[23:0]
FFFFFF
HBLKTOG34_3
Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4F
[23:0]
FFFFFF
HBLKTOG56_3
Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
50
[7:0]
00
HBLKSPTR
HBLK sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
51
[11:0]
FFF
HBLKSCP1
HBLK sequence—Change Position 1.
52
[11:0]
FFF
HBLKSCP2
HBLK sequence—Change Position 2.
53
[11:0]
FFF
HBLKSCP3
HBLK sequence—Change Position 3.
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