参数资料
| 型号： | AD9942BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR SGNL 14B 100CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，14 位 |
| 应用： | 数码相机 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（9x9） |
| 包装： | 带卷 (TR) |
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AD9942
Rev. A | Page 26 of 36
CHANNEL A AND CHANNEL B POWER-UP PROCEDURE
When the AD9942 is powered up, the following sequence is
recommended for Channel A and Channel B (see Figure 27 for
each step).
1.
Turn on the power supplies for the AD9942.
2.
Apply the master clock input, CLI_X, VD_X, and HD_X.
3.
Although the AD9942 contains an on-chip power-on reset,
a software reset of the internal registers is recommended.
Write a 1 to the SW_RST register (Address 0x10), which
resets all the internal registers to their default values. This
bit is self-clearing and is automatically reset to 0.
4.
Reset the Precision Timing core by writing a 0 to the
TGCORE_RSTB register (Address 0x12), then write a l to
the TGCORE_RSTB register. This starts the internal
timing core operation.
5.
Write a 1 to the PREVENTUPDATE register (Address 0x14).
This prevents an update of the serial register data.
6.
Write to the desired registers to configure high speed
timing and horizontal timing.
7.
Write a 3 to the [7:6] TESTMODE register (Address 0x00).
See Table 15.
8.
Write a 1 to the OUT_CONTROL register (Address 0x11).
This allows the outputs to become active after the next
VD_X/HD_X rising edge.
9.
Write a 0 to the PREVENTUPDATE register (Address 0x14).
This allows the serial information to be updated at the
next VD_X/HD_X falling edge. The next VD_X/HD_X
falling edge allows register updates, including updates of
OUT_CONTROL, to occur which enables all clock outputs.
0
52
40
-03
0
VDD
(INPUT)
SERIAL
WRITES
VD_X
(OUTPUT)
1H
ODD FIELD
EVEN FIELD
...
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS
UPDATED AT VD/HD EDGE
H1X/H3X, RG_X
H2X/H4X
tPWR
CLI_X
(INPUT)
HD_X
(OUTPUT)
1V
...
1
2
3
4
5
6
7
8
9
Figure 27. Recommended Power-Up Sequence
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