参数资料
| 型号： | AD9942BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/36页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR SGNL 14B 100CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，14 位 |
| 应用： | 数码相机 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（9x9） |
| 包装： | 带卷 (TR) |
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AD9942
Rev. A | Page 21 of 36
H DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9942
features on-chip output drivers for the RG_X and H1X to H4X
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG-driver currents can be
adjusted for optimum rise and fall time into a particular load by
using the DRVCONTROL register (Address 0x62). The
DRVCONTROL register is divided into five 3-bit values, each
adjustable in 4.1 mA increments. The minimum setting of 0 is
equal to off, or three-state, and the maximum setting of 7 is
equal to 30.1 mA.
As shown in Figure 18, the H2X/H4X outputs are inverses of
H1X. The internal propagation delay resulting from the signal
inversion is less than l ns, which is significantly less than the
typical rise time driving the CCD load. This results in a
H1X/H2X crossover voltage at approximately 50% of the output
swing. The crossover voltage is not programmable.
DIGITAL DATA OUTPUTS
The AD9942 data output phase is programmable using the
DOUTPHASE register (Address 0x64). Any edge from 0 to 47
can be programmed, as shown in Figure 19. The pipeline delay
for the digital data output is shown in Figure 20.
05
24
0-
02
1
FIXED CROSSOVER VOLTAGE
H1X/H3X
H2X/H4X
tPD
H2X/H4X
H1X/H3X
tRISE
tPD << tRISE
Figure 18. H-Clock Inverse Phase Relationship
05
240
-0
22
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
P[0]
P[48] = P[0]
CLI_X
1 PIXEL PERIOD
P[12]
P[24]
P[36]
DOUT
tOD
Figure 19. Digital Output Phase Adjustment
05
240
-023
0123
4567
89
10
11
12
14
15
012
3
H-COUNTER
RESET
VD_X
NOTES
1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
HD_X
CLI_X
XX
X
H COUNTER
(PIXEL COUNTER)
XX
X
Figure 20. Pipeline Delay for Channel A and Channel B Digital Data Output
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