- 您现在的位置：买卖IC网 > PDF目录11768 > AD9981KSTZ-80 (Analog Devices Inc)IC INTERFACE 10BIT ANALOG 80LQFP PDF资料下载
参数资料
| 型号： | AD9981KSTZ-80 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/44页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 10BIT ANALOG 80LQFP |
| 标准包装： | 90 |
| 应用： | 视频 |
| 接口： | 模拟 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
AD9981
Rev. 0 | Page 29 of 44
DETAILED 2-WIRE SERIAL CONTROL REGISTER DESCRIPTIONS
CHIP IDENTIFICATION
0x00
7:0
Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
0x01
7:0
PLL Divide Ratio MSBs
The eight MSBs of the 12-bit PLL divide ratio PLLDIV.
The PLL derives a pixel clock from the incoming
Hsync signal. The pixel clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095 as long as the output frequency
is within range. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency.
VESA has established some standard timing specifi-
cations, which will assist in determining the value for
PLLDIV as a function of horizontal and vertical
display resolution and frame rate (see Table 9).
However, many computer systems do not conform
precisely to the recommendations and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV usually produces one or more vertical noise
bars on the display. The greater the error, the greater
the number of bars produced.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
The AD9981 updates the full divide ratio only when
the LSBs are written. Writing to this register by itself
does not trigger an update.
0x02
7:4
PLL Divide Ratio LSBs
The four LSBs of the 12-bit PLL divide ratio PLLDIV.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
CLOCK GENERATOR CONTROL
0x03
7:6
VCO Range Select
Two bits that establish the operating range of the clock
generator. VCORNGE must be set to correspond to
the desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high
frequencies. For this reason, in order to output low
pixel rates and still get good jitter performance, the
PLL actually operates at a higher frequency but then
divides down the clock rate afterwards. See Table 13
for the pixel rates for each VCO range setting. The
PLL output divisor is automatically selected with the
VCO range setting. The power-up default value is 01.
Table 13. VCO Ranges
VCO Range
Pixel Rates
00
10 to 21
01
21 to 42
10
42 to 84
11
84 to 95
0x03
5:3
Charge Pump Current
Three bits that establish the current driving the loop
filter in the clock generator. The current must be set to
correspond with the desired operating frequency. The
power-up default value is current = 001.
Table 14. Charge Pump Currents
Ip2
Ip1
Ip0
Current
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
0x03
2
External Clock Enable
This bit determines the source of the pixel clock.
Table 15. External Clock Select Settings
EXTCLK
Function
0
Internally generated clock
1
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external EXTCLK input pin. In
this mode, the PLL Divide Ratio (PLLDIV) is ignored.
The clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
相关PDF资料 |
PDF描述 |
|---|---|
| PIC16LF1906-I/MV | MCU PIC 512B FLASH XLP 28-UQFN |
| VI-B41-IX-F1 | CONVERTER MOD DC/DC 12V 75W |
| MS27505E21B39P | CONN RCPT 39POS BOX MNT W/PINS |
| PIC16F721-I/P | MCU PIC 4K FLASH 20-DIP |
| 5227079-6 | CONN PLUG BNC RG55,223 CRIMP AU |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9981KSTZ-95 | 功能描述:IC INTERFACE 10BIT ANALOG 80LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9983A | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:Advantiv® 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
发布紧急采购，3分钟左右您将得到回复。