参数资料
型号: AD9981KSTZ-80
厂商: Analog Devices Inc
文件页数: 41/44页
文件大小: 0K
描述: IC INTERFACE 10BIT ANALOG 80LQFP
标准包装: 90
应用: 视频
接口: 模拟
电源电压: 3.13 V ~ 3.47 V
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(14x14)
包装: 管件
安装类型: 表面贴装
AD9981
Rev. 0 | Page 6 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04739-002
2
BAIN0
3
GND
4
BAIN1
7
GND
6
GAIN0
5
VD (3.3V)
1
VD (3.3V)
8
SOGIN0
9
VD (3.3V)
10
GAIN1
12
SOGIN1
13
VD (3.3V)
14
RAIN0
15
GND
16
RAIN1
17
PWRDN
18
REFLO
19
REFCM
20
REFHI
11
GND
59
58
57
54
55
56
60
53
52
BLUE <4>
BLUE <5>
BLUE <6>
BLUE <9>
BLUE <8>
BLUE <7>
BLUE <3>
GND
VDD (3.3V)
51
GREEN <0>
49
GREEN <2>
48
GREEN <3>
47
GREEN <4>
46
GREEN <5>
45
GREEN <6>
44
GREEN <7>
43
GREEN <8>
42
GREEN <9>
41
DAVDD (1.8)
50
GREEN <1>
21
O/E
FIELD
22
VSOU
T
/A
0
23
HS
OUT
24
SOGOUT
25
DATACK
26
V
DD
(
3
.3V)
27
GND
28
RE
D
<9
>
29
RE
D
<8
>
30
RE
D
<7
>
31
RE
D
<6
>
32
RE
D
<5
>
33
RE
D
<4
>
34
RE
D
<3
>
35
RE
D
<2
>
36
RE
D
<1
>
37
RE
D
<0
>
38
V
DD
(
3
.3V)
39
GND
40
GND
80
GND
79
P
VD
(
1
.8V)
78
FILT
77
GND
76
P
VD
(
1
.8V)
75
GND
74
P
VD
(
1
.8V)
73
CCLAMP
72
E
X
T
CLK/COAS
T
71
VSYN
C
0
70
HS
Y
NC0
69
VSYN
C
1
68
HS
Y
NC1
67
SC
L
66
SD
A
65
GND
64
V
DD
(3
.3
V
)
63
BLUE
<0
>
62
BLUE
<1
>
61
BLUE
<2
>
PIN 1
AD9981
TOP VIEW
(Not to Scale)
Figure 2. Top View (Pins Down)
Table 3. Complete Pinout List
Pin Type
Mnemonic
Function
Value
Pin No.
Inputs
RAIN0
Channel 0 Analog Input for Converter R
0.0 V to 1.0 V
14
RAIN1
Channel 1 Analog Input for Converter R
0.0 V to 1.0 V
16
GAIN0
Channel 0 Analog Input for Converter G
0.0 V to 1.0 V
6
GAIN1
Channel 1 Analog Input for Converter G
0.0 V to 1.0 V
10
BAIN0
Channel 0 Analog Input for Converter B
0.0 V to 1.0 V
2
BAIN1
Channel 1 Analog Input for Converter B
0.0 V to 1.0 V
4
HSYNC0
Horizontal Sync Input for Channel 0
3.3 V CMOS
70
HSYNC1
Horizontal Sync Input for Channel 1
3.3 V CMOS
68
VSYNC0
Vertical Sync Input for Channel 0
3.3 V CMOS
71
VSYNC1
Vertical Sync Input for Channel 1
3.3 V CMOS
69
SOGIN0
Input for Sync-on-Green Channel 0
0.0 V to 1.0 V
8
SOGIN1
Input for Sync-on-Green Channel 1
0.0 V to 1.0 V
12
EXTCK
External Clock Input
3.3 V CMOS
CLAMP
External Clamp Input Signal
3.3 V CMOS
73
COAST
External PLL Coast Signal Input
3.3 V CMOS
PWRDN
Power-Down Control
3.3 V CMOS
17
Outputs
RED [9:0]
Outputs of Converter R, Bit 9 is the MSB
3.3 V CMOS
28 to 37
GREEN [9:0]
Outputs of Converter G, Bit 9 is the MSB
3.3 V CMOS
42 to 51
BLUE [9:0]
Outputs of Converter B, Bit 9 is the MSB
3.3 V CMOS
54 to 63
DATACK
Data Output Clock
3.3 V CMOS
25
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