参数资料
| 型号： | AD9995KCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/60页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 标准包装： | 1 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 30mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 56-LFCSP-VQ（8x8） |
| 包装： | 托盘 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
AD9995
–12–
AD9995
–13–
HORIZONTAL CLAMPING AND BLANKING
The AD9995’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual control
is provided for CLPOB, PBLK, and HBLK during the different
regions of each field.This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 9.These two signals are independently pro-
grammed using the registers in Table III. SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the first and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
A separate pattern for CLPOB and PBLK may be programmed
for every 10 V-sequences. As described in the Vertical Timing
Generation section, up to 10 separate V-sequences can be created,
each containing a unique pulse pattern for CLPOB and PBLK.
Figure 9 shows how the sequence change positions divide the
readout field into different regions. A different V-sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to be changed accordingly with each change in the vertical timing.
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 10 is simi-
lar to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is a
polarity control HBLKMASK that designates the polarity of the
horizontal clock signals H1–H4 during the blanking period. Set-
ting HBLKMASK high will set H1 = H3 = low and H2 = H4 =
high during the blanking, as shown in Figure 11. As with the
CLPOB and PBLK signals, HBLK registers are available in each
V-sequence, allowing different blanking signals to be used with
different vertical timing sequences.
(3)
(2)
(1)
HD
CLPOB
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION
. . .
ACTIVE
Figure 9. Clamp and Pre-Blank Pulse Placement
Table III. CLPOB and PBLK Pattern Registers
Register
Length
Range
Description
SPOL
1b
High/Low
Starting Polarity of CLPOB/PBLK for V-Sequence 0–9
TOG1
12b
0–4095 Pixel Location
First Toggle Position within Line for V-Sequence 0–9
TOG2
12b
0–4095 Pixel Location
Second Toggle Position within Line for V-Sequence 0–9
Table IV. HBLK Pattern Registers
Register
Length
Range
Description
HBLKMASK
1b
High/Low
Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High)
HBLKALT
2b
0–3 Alternation Mode
Enables Odd/Even Alternation of HBLK Toggle Positions 0 =
Disable Alternation. 1 = TOG1–TOG2 Odd,TOG3–TOG6 Even.
2 = 3 = TOG1–TOG2 Even,TOG3–TOG6 Odd
HBLKTOG1
12b
0–4095 Pixel Location
First Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG2
12b
0–4095 Pixel Location
Second Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG3
12b
0–4095 Pixel Location
Third Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG4
12b
0–4095 Pixel Location
Fourth Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG5
12b
0–4095 Pixel Location
Fifth Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG6
12b
0–4095 Pixel Location
Sixth Toggle Position within Line for Each V-Sequence 0–9
REV. 0
OBSOLETE
相关PDF资料 |
PDF描述 |
|---|---|
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| ADATE305BSVZ | IC DCL ATE 250MHZ DUAL 100TQFP |
| ADAU1328BSTZ | IC CODEC 24BIT 2ADC/8DAC 48LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9995KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 传感器和探测器接口 系列:- 其它有关文件:Automotive Product Guide 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:74 系列:- 类型:触控式传感器 输入类型:数字 输出类型:数字 接口:JTAG，串行 电流 - 电源:100µA 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:20-TSSOP 包装:管件 |
| AD9995KCPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9996BBCZ | 制造商:Rochester Electronics LLC 功能描述:14B 40 MSPS AFETG CONVERTER - Bulk |
| AD9996BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD-9FT4-B2 | 制造商:Pan Pacific 功能描述: |
发布紧急采购，3分钟左右您将得到回复。