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参数资料
| 型号： | ADE5166ASTZF62-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 110/156页 |
| 文件大小： | 0K |
| 描述： | IC METER/8052/RTC/LCD DRV 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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ADE5166/ADE5169/ADE5566/ADE5569
ECON—Flash Control SFR
Programming the flash memory is done through the flash control
SFR (ECON, Address 0xB9). This SFR allows the user to read,
write, erase, or verify the 62 kB of flash memory. As a method
of security, a key must be written to the flash key SFR
(FLSHKY, Address 0xBA) to initiate any user access to the flash
memory. Upon completion of the flash memory operation, the
FLSHKY SFR is reset so that it must be written to before
another flash memory operation. Requiring the key to be set
before an access to the flash memory decreases the likelihood of
user code or data being overwritten by a runaway program.
Table 105. Flash Control SFR (ECON, Address 0xB9)
Data Sheet
The program counter, PC, is held on the instruction where
the ECON SFR is written to until the flash memory controller
finishes the requested operation. Then the PC increments to con-
tinue with the next instruction. Any interrupt requests that occur
while the flash controller is performing an operation are not
handled until the flash operation is complete. All peripherals,
such as timers and counters, continue to operate as configured
throughout the flash memory access.
Bit
[7:0]
Mnemonic
ECON
Default
0
Value
1
Description
Write byte. The value in the EDATA SFR (Address 0xBC) is written to the flash memory, at the
page address given by EADRH (Address 0xC7) and EADRL (Address 0xC6). Note that the byte
being addressed must be pre-erased.
2
3
4
5
6
7
8
Erase page. A 512-byte page of flash memory address is erased. The page is selected by the
address in the EADRH and EADRL SFRs. Any address in the page can be written to EADRH and
EADRL to select it for erasure.
Erase all. All 62 kB of the available flash memory are erased. Note that this command is used
during serial mode and parallel download mode but should not be executed by user code.
Read byte. The byte in the flash memory, addressed by EADRH and EADRL, is read into EDATA.
Reserved.
Reserved.
Reserved.
Protect code (see the Protecting the Flash Memory section).
Table 1 06. Flash Key SFR (FLSHKY, Address 0xBA)
Bit
[7:0]
Mnemonic
FLSHKY
Default
0xFF
Description
The contents of this SFR are compared to the flash key, 0x3B. If the two values match, the next ECON SFR
operation is allowed (see the Protecting the Flash Memory section).
Table 107. Flash Protection Key SFR (PROTKY, Address 0xBB)
Bit
[7:0]
Mnemonic
PROTKY
Default
0xFF
Description
The contents of this SFR are compared to the flash memory location at Address 0xF7EB. If the two values
match, the update of the write/erase and read protection setup is allowed (see the Protecting the Flash
Memory section).
If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison.
The PROTKY SFR is also used to write the protection key in the flash. This is done by writing the desired
value in PROTKY and writing 0x08 in the ECON SFR. This operation can be done only once.
Table 1 08. Flash Dat a SFR (EDATA, Address 0xBC)
Bit
[7:0]
Mnemonic
EDATA
Default
0
Description
Flash pointer data.
Table 1 09. Flash Low Byte Address SFR (EADRL, Address 0xC6)
Bit
[7:0]
Mnemonic
EADRL
Default
0
Description
Flash pointer low byte address.
Table 110. Flash High Byte Address SFR (EADRH, Address 0xC7)
Bit
[7:0]
Mnemonic
EADRH
Default
0
Description
Flash pointer high byte address.
Rev. D | Page 110 of 156
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