参数资料
型号: ADE5166ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 42/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
ADE5166/ADE5169/ADE5566/ADE5569
ENERGY MEASUREMENT REGISTERS
Table 32. Energy Measurement Register List
Data Sheet
Address
Length
Signed/
MADDPT[6:0]
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Mnemonic
WATTHR
RWATTHR
LWATTHR
VARHR 1
RVARHR 1
LVARHR 1
VAHR
R/W
R
R
R
R
R
R
R
(Bits)
24
24
24
24
24
24
24
Unsigned
S
S
S
S
S
S
S
Default
0
0
0
0
0
0
0
Description
Reads the Wh accumulator without reset.
Reads the Wh accumulator with reset.
Reads the Wh accumulator synchronous to line cycle.
Reads the varh accumulator without reset.
Reads the varh accumulator with reset.
Reads the varh accumulator synchronous to line cycle.
Reads VAh accumulator without reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates I rms .
0x08
RVAHR
R
24
S
0
Reads VAh accumulator with reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates I rms .
0x09
LVAHR
R
24
S
0
Reads VAh accumulator synchronous to line cycle. If the VARMSCFCON
bit in the MODE2 register (Address 0x0C) is set, this register accumulates
I rms .
0x0A
0x0B
0x0C
0x0D
PER_FREQ
MODE1
MODE2
WAVMODE
R
R/W
R/W
R/W
16
8
8
8
U
U
U
U
0
0x06
0x40
0
Reads line period or frequency register, depending on MODE2 register.
Sets basic configuration of energy measurement (see Table 33).
Sets basic configuration of energy measurement (see Table 34).
Sets configuration of Waveform Sample 1 and Waveform Sample 2
(see Table 35).
0x0E
0x0F
NLMODE
ACCMODE
R/W
R/W
8
8
U
U
0
0
Sets level of energy no load thresholds (see Table 36).
Sets configuration of watt and var accumulation and various tamper
alarms (see Table 37).
0x10
0x11
PHCAL
ZXTOUT
R/W
R/W
8
12
S
U
0x40
0xFFF
Sets phase calibration register (see the Phase Compensation section).
Sets timeout for zero-crossing timeout detection (see the Zero-
Crossing Timeout section).
0x12
LINCYC
R/W
16
U
0xFFFF
Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR
accumulators.
0x13
SAGCYC
R/W
8
U
0xFF
Sets number of half-line cycles for SAG detection (see the Line
Voltage SAG Detection section).
0x14
SAGLVL
R/W
16
U
0
Sets detection level for SAG detection (see the Line Voltage SAG
Detection section).
0x15
IPKLVL
R/W
16
U
0xFFFF
Sets peak detection level for current peak detection (see the Peak
Detection section).
0x16
VPKLVL
R/W
16
U
0xFFFF
Sets peak detection level for voltage peak detection (see the Peak
Detection section).
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
IPEAK
RSTIPEAK
VPEAK
RSTVPEAK
GAIN
IBGAIN 2
WGAIN
VARGAIN 1
VAGAIN
WATTOS
VAROS 1
IRMSOS
VRMSOS
WDIV
VARDIV 1
VADIV
CF1NUM
CF1DEN
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
24
24
24
24
8
12
12
12
12
16
16
12
12
8
8
8
16
16
U
U
U
U
U
S
S
S
S
S
S
S
S
U
U
U
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x003F
Reads current peak level without reset (see the Peak Detection section).
Reads current peak level with reset (see the Peak Detection section).
Reads voltage peak level without reset (see the Peak Detection section).
Reads voltage peak level with reset (see the Peak Detection section).
Sets PGA gain of analog inputs (see Table 38).
Sets matching gain for I PB current input.
Sets watt gain register.
Sets var gain register.
Sets VA gain register.
Sets watt offset register.
Sets var offset register.
Sets current rms offset register.
Sets voltage rms offset register.
Sets watt energy scaling register.
Sets var energy scaling register.
Sets VA energy scaling register.
Sets CF1 numerator register.
Sets CF1 denominator register.
Rev. D | Page 42 of 156
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