- 您现在的位置：买卖IC网 > PDF目录4596 > ADE5166ASTZF62-RL (Analog Devices Inc)IC METER/8052/RTC/LCD DRV 64LQFP PDF资料下载
参数资料
| 型号： | ADE5166ASTZF62-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/156页 |
| 文件大小： | 0K |
| 描述： | IC METER/8052/RTC/LCD DRV 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页
ADE5166/ADE5169/ADE5566/ADE5569
EPSR
FPSR
ESAG
FSAG
Data Sheet
EVADC
FVADC
FPSM
EPSM
TRUE?
PENDING PSM
INTERRUPT
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
EPSR
FPSR
PS2
RESERVED
FPSM
PTI
ESAG
FSAG
ES2
RESERVED
RESERVED
PSI
EVADC
FVADC
EADE
EBAT
FBAT
ETI
EBSO
FBSO
EPSM
EVDCIN
FVDCIN
ESI
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
Figure 33. Power Supply Management Interrupt Sources
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to generate a PSM interrupt when the source of V SWOUT changes
from V DD to V BAT , indicating battery switchover. Setting the EBSO
bit (Bit 1) in the power management interrupt enable SFR (IPSME,
Address 0xEC) enables this event to generate a PSM interrupt
(see Table 21).
The ADE5166/ADE5169/ADE5566/ADE5569 can also be con-
figured to generate an interrupt when the source of V SWOUT changes
from V BAT to V DD , indicating that the V DD power supply has been
restored. Setting the EPSR bit (Bit 7) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event to
generate a PSM interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO (Bit 1)
and FPSR (Bit 7), are set regardless of whether the respective
enable bits are set. The battery switchover and power supply
restore event flags (FBSO and FPSR) are latched. These events
must be cleared by writing 0 to these bits. The VSWSOURCE bit
(Bit 6) in the peripheral configuration SFR (PERIPH, Address
0xF4) tracks the source of V SWOUT . The bit is set when V SWOUT is
connected to V DD and cleared when V SWOUT is connected to V BAT .
V DCIN ADC PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to generate a PSM interrupt when V DCIN changes magnitude by
more than a configurable threshold. This threshold is set in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3),
as described in Table 51. See the External Voltage Measurement
section for more information. Setting the EVADC bit (Bit 3) in
the power management interrupt enable SFR (IPSME, Address
0xEC) enables this event to generate a PSM interrupt.
The V DCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in V DCIN . Conversions can also be initiated by writing to
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Table 52. The FVADC flag indicates when a V DCIN
measurement is ready. See the External Voltage Measurement
section for details on how V DCIN is measured.
V BAT Monitor PSM Interrupt
The V BAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in V BAT . The FBAT bit (Bit 2 in the IPSMF SFR) is
set when the battery level is lower than the threshold set in the
battery detection threshold SFR (BATVTH, Address 0xFA),
described in Table 53; or when a new measurement is ready in
the battery ADC value SFR (BATADC, Address 0xDF), described
in Table 55. See the Battery Measurement section for more infor-
mation. Setting the EBAT bit (Bit 2) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event
to generate a PSM interrupt.
V DCIN Monitor PSM Interrupt
The V DCIN voltage is monitored by a comparator. The FVDCIN
bit (Bit 0) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the V DCIN input level is lower than 1.2 V.
Setting the EVDCIN bit (Bit 0) in the IPSME SFR enables this
event to generate a PSM interrupt. This event, which is associated
with the SAG monitoring, can be used to detect that a power
supply (V DD ) is compromised and to trigger further actions prior to
initiating a switch from V DD to V BAT .
Rev. D | Page 32 of 156
相关PDF资料 |
PDF描述 |
|---|---|
| ADE5166ASTZF62 | IC METER/8052/RTC/LCD DRV 64LQFP |
| NCP699SN28T1G | IC REG LDO 2.8V 240MA 5TSOP |
| RSC50DRYN-S13 | CONN EDGECARD 100POS .100 EXTEND |
| LFEC3E-4QN208I | IC FPGA 3.1KLUTS 208PQFP |
| KSZ8995MAI | IC SWITCH 5-PORT 10/100 128PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADE5169 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
| ADE5169ASTZF62 | 功能描述:IC METER/8052/RTC/LCD DR 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5169ASTZF62-RL | 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5566 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
| ADE5566ASTZF62 | 功能描述:IC ENERGY METERING 1PHASE 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
发布紧急采购，3分钟左右您将得到回复。