参数资料
型号: ADE5166ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 76/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
ADE5166/ADE5169/ADE5566/ADE5569
Table 51. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3)
Data Sheet
Bit
[7:6]
[5:3]
Mnemonic
Reserved
TEMP_DIFF
Default
00
00
Description
Reserved.
Difference threshold between last temperature measurement interrupting 8052 and new
temperature measurement that should interrupt 8052.
TEMP_DIFF
000
001
010
011
100
101
110
111
Result
No interrupt
1 LSB (~ 0.8°C)
2 LSB (~ 1.6°C)
3 LSB (~ 2.4°C)
4 LSB (~ 3.2°C)
5 LSB (~ 4°C)
6 LSB (~ 4.8°C)
Every temperature measurement
[2:0]
VDCIN_DIFF
00
Difference threshold between the last external voltage measurement interrupting 8052 and the new
external voltage measurement that should interrupt 8052.
VDCIN_DIFF
000
001
010
011
100
101
110
111
Result
No interrupt
1 LSB (~ 120 mV)
2 LSB (~ 240 mV)
3 LSB (~ 360 mV)
4 LSB (~ 480 mV)
5 LSB (~ 600 mV)
6 LSB (~ 720 mV)
Every V DCIN measurement
Table 52. Start ADC Measurement SFR (ADCGO, Address 0xD8)
Bit
7
Bit Address
0xDF
Mnemonic
PLLACK
Default
0
Description
Set this bit to clear the PLL fault bit, PLL_FLT (Bit 4), in the PERIPH SFR (Address 0xF4).
A PLL fault is generated if a reset is caused because the PLL lost lock.
[6:3]
2
0xDE to 0xDB
0xDA
Reserved
VDCIN_ADC_GO
0000
0
Reserved.
Set this bit to initiate an external voltage measurement. This bit is cleared when
the measurement request is received by the ADC.
1
0xD9
TEMP_ADC_GO
0
Set this bit to initiate a temperature measurement. This bit is cleared when the
measurement request is received by the ADC.
0
0xD8
BATT_ADC_GO
0
Set this bit to initiate a battery measurement. This bit is cleared when the
measurement request is received by the ADC.
Table 53. Battery Detection Threshold SFR (BATVTH, Address 0xFA)
Bit
[7:0]
Mnemonic
BATVTH
Default
0
Description
The battery ADC value is compared to this register, the battery detection threshold register.
If BATADC is lower than the threshold, an interrupt is generated.
Table 54. V DCIN ADC Value SFR (VDCINADC, Address 0xEF)
Bit
[7:0]
Mnemonic
VDCINADC
Default
0
Description
The V DCIN ADC value in this register is updated when an ADC interrupt occurs.
Table 55. Battery ADC Value SFR (BATADC, Address 0xDF)
Bit
[7:0]
Mnemonic
BATADC
Default
0
Description
The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 56. Temperature ADC Value SFR (TEMPADC, Address 0xD7)
Bit
[7:0]
Mnemonic
TEMPADC
Default
0
Description
The temperature ADC value in this register is updated when an ADC interrupt occurs.
Rev. D | Page 76 of 156
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