参数资料
型号: ADE5166ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 80/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)

ADE5166/ADE5169/ADE5566/ADE5569
8052 MCU CORE ARCHITECTURE
Data Sheet
The ADE5166/ADE5169/ADE5566/ADE5569 have an 8052 MCU
core and use the 8051 instruction set. Some of the standard 8052
peripherals, such as the UART, have been enhanced. This section
describes the standard 8052 core and enhancements that have
been made to it in the ADE5166/ADE5169/ADE5566/ADE5569.
256 BYTES
GENERAL-
PURPOSE
62kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
ENERGY
MEASUREMENT
POWER
MANAGEMENT
RTC
The special function register (SFR) space is mapped into the upper
128 bytes of internal data memory space and is accessed by direct
addressing only. It provides an interface between the CPU and all
on-chip peripherals. See Figure 81 for a block diagram showing
the programming model of the ADE5166/ADE5169/ADE5566/
ADE5569 via the SFR area.
RAM
REGISTER
BANKS
8051-COMPATIBLE
CORE
PC IR
2kB XRAM
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
LCD DRIVER
TEMPERATURE
ADC
BATTERY
ADC
OTHER ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
All registers except the program counter (PC), instruction register
(IR), and the four general-purpose register banks reside in the
SFR area. The SFRs include control, configuration, and data
registers that provide an interface between the CPU and all on-
chip peripherals.
MCU REGISTERS
The registers used by the MCU are summarized in Table 57.
Table 57. 8051 SFRs
TIMERS
Figure 81. Block Diagram Showing Programming Model via the SFRs
SFR
ACC
B
PSW
PCON
DPL
DPH
DPTR
SP
SPH
STCON
CFG
Address
0xE0
0xF0
0xD0
0x87
0x82
0x83
0x82 and 0x83
0x81
0xB7
0xBF
0xAF
Bit Addressable
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Description
Accumulator.
Auxiliary math.
Program status word (see Table 58).
Program control (see Table 59).
Data pointer low (see Table 60).
Data pointer high (see Table 61).
Data pointer (see Table 62).
Stack pointer (see Table 63).
Stack pointer high (see Table 64).
Stack boundary (see Table 65).
Configuration (see Table 66).
Table 58. Program Status Word SFR (PSW, Address 0xD0)
Bit
Bit
Mnemonic
Description
Address
7
6
5
[4:3]
0xD7
0xD6
0xD5
0xD4,
CY
AC
F0
RS1, RS0
Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
Auxiliary carry flag. Modified by ADD and ADDC instructions.
General-purpose flag available to the user.
Register bank select bits.
0xD3
RS1
0
0
1
1
RS0
0
1
0
1
Selected Bank
0
1
2
3
2
1
0
0xD2
0xD1
0xD0
OV
F1
P
Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
General-purpose flag available to the user.
Parity bit. The number of bits set in the accumulator added to the value of the parity bit is always an
even number.
Rev. D | Page 80 of 156
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