参数资料
型号: ADE5166ASTZF62
厂商: Analog Devices Inc
文件页数: 100/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘

ADE5166/ADE5169/ADE5566/ADE5569
LCD DRIVER
Using shared pins, the LCD module is capable of directly driving
an LCD panel of 17 × 4 segments without compromising any
ADE5166/ADE5169/ADE5566/ADE5569 functions. It is capable
of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD wave-
form voltages generated through internal charge pump circuitry
support up to 5 V LCDs. An external resistor ladder for LCD
waveform voltage generation is also supported.
Each ADE5166/ADE5169/ADE5566/ADE5569 has an embedded
LCD control circuit, driver, and power supply circuit. The LCD
module is functional in all operating modes (see the Operating
Modes section) and can store up to four different screens in
memory for scrolling purposes.
Data Sheet
LCD REGISTERS
There are eight LCD control registers that configure the driver
for the specific type of LCD in the end system and set up the user
display preferences. The LCD configuration SFR (LCDCON,
Address 0x95), LCD Configuration X SFR (LCDCONX,
Address 0x9C), and LCD Configuration Y SFR (LCDCONY,
Address 0xB1) contain general LCD driver configuration infor-
mation including the LCD enable and reset, as well as the method
of LCD voltage generation and multiplex level. The LCD clock SFR
(LCDCLK, Address 0x96) configures timing settings for LCD
frame rate and blink rate. LCD pins are configured for LCD
functionality in the LCD segment enable SFR (LCDSEGE,
Address 0x97) and the LCD Segment Enable 2 SFR (LCDSEGE2,
Address 0xED).
Table 90. LCD Driver SFRs
SFR Address
0x95
0x96
0x97
0x9C
0xAC
0xAE
0xB1
0xED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mnemonic
LCDCON
LCDCLK
LCDSEGE
LCDCONX
LCDPTR
LCDDAT
LCDCONY
LCDSEGE2
Description
LCD configuration (see Table 91).
LCD clock (see Table 95).
LCD segment enable (see Table 98).
LCD Configuration X (see Table 92).
LCD pointer (see Table 99).
LCD data (see Table 100).
LCD Configuration Y (see Table 94).
LCD Segment Enable 2 (see Table 101).
Table 91. LCD Configuration SFR (LCDCON, Address 0x95)
Bit
7
6
5
Mnemonic
LCDEN
LCDRST
BLINKEN
Default
0
0
0
Description
LCD enable. If this bit is set, the LCD driver is enabled.
LCD data registers reset. If this bit is set, the LCD data registers are reset to 0.
Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by
BLKMOD (Bits[7:6]) and BLKFREQ (Bits[5:4]) in the LCD clock SFR (LCDCLK, Address 0x96).
4
LCDPSM2
0
Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by
setting REF_BAT_EN (Bit 3) in the peripheral configuration SFR (PERIPH, Address 0xF4) to allow LCD
operation in PSM2.
LCDPSM2
0
1
Result
The LCD is disabled or enabled in PSM2 by LCDEN (Bit 7)
The LCD is disabled in PSM2 regardless of LCDEN setting
3
2
[1:0]
CLKSEL
BIAS
LMUX
0
0
01
LCD clock selection.
CLKSEL
Result
0
f LCDCLK = 2048 Hz
1
f LCDCLK = 128 Hz
Bias mode.
BIAS
Result
0
1/2
1
1/3
LCD multiplex level.
LMUX
Result
00
Reserved
01
2× multiplexing; COM3/FP27 is used as FP27, and COM2/FP28 is used as FP28
10
3× multiplexing; COM3/FP27 is used as FP27, and COM2/FP28 is used as COM2
11
4× multiplexing; COM3/FP27 is used as COM3, and COM2/FP28 is used as COM2
Rev. D | Page 100 of 156
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