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参数资料
型号： ADE5166ASTZF62
厂商： Analog Devices Inc
文件页数： 72/156页
文件大小： 0K
描述： IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告： Product Discontinuance 27/Oct/2011
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
ADE5166/ADE5169/ADE5566/ADE5569
Line Cycle Apparent Energy Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are designed with
a special apparent energy accumulation mode that simplifies the
calibration process. By using the on-chip, zero-crossing detection,
the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the
apparent power signal in the LVAHR register (Address 0x09) for
an integral number of half cycles, as shown in Figure 78. The line
cycle apparent energy accumulation mode is always active.
The number of half-line cycles is specified in the LINCYC
register (Address 0x12), which is an unsigned 16-bit register.
The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate
apparent power for up to 65,535 combined half cycles. Because
the apparent power is integrated on the same integral number
of line cycles as the line active register and reactive energy register,
these values can easily be compared. The energies are calculated
more accurately because of this precise timing control and provide
all the information needed for reactive power and power factor
calculation.
At the end of an energy calibration cycle, the CYCEND flag (Bit 2)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.
If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) is set, the 8052 core has a pending
ADE interrupt.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVAHR register (Address 0x09) is reset and a
new accumulation starts at the next zero crossing. The number of
half-line cycles is then counted until LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line apparent energy accumulation uses the same signal path as
the apparent energy accumulation. The LSB size of these two
registers is equivalent.
Data Sheet
Apparent Power No Load Detection
The ADE5166/ADE5169/ADE5566/ADE5569 include a no load
threshold feature on the apparent power that eliminates any creep
effects in the meter. The ADE5166/ADE5169/ADE5566/ADE5569
accomplish this by not accumulating energy if the multiplier output
is below the no load threshold. When the apparent power is
below the no load threshold, the VANOLOAD flag (Bit 2) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
If the VANOLOAD bit (Bit 2) is set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
VANOLOAD status bit is cleared (see the Energy Measurement
Interrupts section).
The no load threshold level can be selected by setting the
VANOLOAD bits (Bits[5:4]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.030%, 0.015%, and 0.0075% of the
full-scale output frequency of the multiplier, respectively.
This no load threshold can also be applied to the I rms pulse
output when selected. In this case, the level of the no load
threshold is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy
meter, the ADE5166/ADE5169/ADE5566/ADE5569 are capable
of accumulating the ampere-hours instead of apparent power into
the VAHR (Address 0x07), RVAHR (Address 0x08), and LVAHR
(Address 0x09) registers. When VARMSCFCON (Bit 3) of the
MODE2 register (Address 0x0C) is set, the VAHR, RVAHR,
and LVAHR registers and the input for the digital-to-frequency
converter accumulate I rms instead of apparent power. All the signal
processing and calibration registers available for apparent power
and energy accumulation remain the same when ampere-hour
accumulation is selected. However, the scaling difference between
I rms and apparent power requires independent values for gain cali-
bration in the VAGAIN (Address 0x1F), VADIV (Address 0x26),
CFxNUM (Address 0x27 and Address 0x29), and CFxDEN
(Address 0x28 and Address 0x2A) registers.
APPARENT POWER
OR I rms
%
+
+
48
0
LVAHR REGISTER IS
VADIV[7:0]
UPDATED EVERY LINCYC
ZERO CROSSING WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
LPF1
23
0
FROM
VOLTAGE CHANNEL
ADC
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
LVAHR[23:0]
LINCYC[15:0]
Figure 78. Line Cycle Apparent Energy Accumulation Mode
Rev. D | Page 72 of 156
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相关代理商/技术参数
参数描述
ADE5166ASTZF62-RL 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:*
ADE5169 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
ADE5169ASTZF62 功能描述:IC METER/8052/RTC/LCD DR 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:*
ADE5169ASTZF62-RL 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:*
ADE5566 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
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