参数资料
型号: ADE5166ASTZF62
厂商: Analog Devices Inc
文件页数: 55/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
Data Sheet
Figure 56 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than MCLK/160 × ZXTOUT seconds.
12-BIT INTERNAL
REGISTER VALUE
ZXTOUT
VOLTAGE
CHANNEL
ADE5166/ADE5169/ADE5566/ADE5569
Line Voltage SAG Detection
In addition to detection of the loss of the line voltage signal
(zero crossing), the ADE5166/ADE5169/ADE5566/ADE5569 can
also be programmed to detect when the absolute value of the line
voltage drops below a certain peak value for a number of line
cycles. This condition is illustrated in Figure 57.
VOLTAGE CHANNEL
FULL SCALE
SAGLVL[15:0]
SAG IS RESET LOW
WHEN VOLTAGE
ZXTO
FLAG
BIT
SAG FLAG
SAGCYC[7:0] = 0x04
3 LINE CYCLES
CHANNEL EXCEEDS
SAGLVL[15:0] AND
SAG FLAG IS RESET
Figure 56. Zero-Crossing Timeout Detection
Period or Frequency Measurements
The ADE5166/ADE5169/ADE5566/ADE5569 provide the period
or frequency measurement of the line. The period or frequency
measurement is selected by clearing or setting the FREQSEL bit
(Bit 1) in the MODE2 register (Address 0x0C). The period/
frequency register, PER_FREQ (Address 0x0A), is an unsigned
16-bit register that is updated every period. If LPF1 is enabled,
a settling time of 1.8 sec is associated with this filter before the
measurement is stable.
When the period measurement is selected, the measurement has a
2.44 μs/LSB (4.096 MHz/10) resolution, which represents 0.014%
when the line frequency is 60 Hz. When the line frequency is
60 Hz, the value of the period register is approximately 0d6827.
The length of the register enables the measurement of line fre-
quencies as low as 12.5 Hz. The period register is stable at ±1 LSB
when the line is established and the measurement does not change.
When the frequency measurement is selected, the measurement
has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which
represents 0.104% when the line frequency is 60 Hz. When the
line frequency is 60 Hz, the value of the frequency register is 0d960.
The frequency register is stable at ±4 LSB when the line is estab-
lished and the measurement does not change.
Figure 57. SAG Detection
Figure 57 shows the line voltage falling below a threshold that
is set in the SAG level register (SAGLVL, Address 0x14[15:0])
for three line cycles. The quantities 0 and 1 are not valid for the
SAGCYC register, and the contents represent one more than the
desired number of full line cycles. For example, when the SAG
cycle register (SAGCYC, Address 0x13[7:0]) contains 0x04, FSAG
(Bit 5) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set at the end of the third line cycle after the line
voltage falls below the threshold. If the SAG enable bit (ESAG,
Bit 5) in the power management interrupt enable SFR (IPSME,
Address 0xEC) is set, the 8052 core has a pending power supply
management interrupt. The PSM interrupt stays active until the
FSAG bit is cleared (see the Power Supply Management (PSM)
Interrupt section).
In Figure 57, the SAG flag (FSAG) is set on the fifth line cycle
after the signal on the voltage channel first drops below the
threshold level.
SAG Level Set
The 2-byte contents of the SAG level register (SAGLVL,
Address 0x14) are compared to the absolute value of the output
from LPF1. Therefore, when LPF1 is enabled, writing 0x2038 to the
SAG level register puts the SAG detection level at full scale (see
Figure 57). Writing 0x00 or 0x01 puts the SAG detection level
at 0. The SAG level register is compared to the input of the ZX
detection, and detection is made when the ZX input falls below the
contents of the SAG level register.
Rev. D | Page 55 of 156
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