参数资料
型号: ADE5166ASTZF62
厂商: Analog Devices Inc
文件页数: 29/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
Data Sheet
Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
7
Bit Address
0xFF
Mnemonic
FPSR
Default
0
Description
Power supply restored interrupt flag. Set when the V DD power supply has been restored.
This occurs when the source of V SWOUT changes from V BAT to V DD .
6
5
4
3
0xFE
0xFD
0xFC
0xFB
FPSM
FSAG
Reserved
FVADC
0
0
0
0
PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
This bit must be kept at 0 for proper operation.
V DCIN ADC monitor interrupt flag. Set when V DCIN changes by VDCIN_DIFF or when the V DCIN
measurement is ready.
2
0xFA
FBAT
0
V BAT monitor interrupt flag. Set when V BAT falls below BATVTH or when V BAT measurement is
ready.
1
0
0xF9
0xF8
FBSO
FVDCIN
0
0
Battery switchover interrupt flag. Set when V SWOUT switches from V DD to V BAT .
V DCIN monitor interrupt flag. Set when V DCIN falls below 1.2 V.
Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit
[7:2]
[1:0]
Mnemonic
Reserved
BATPRG
Default
0
0
Description
These bits must be kept at 0 for proper operation.
Control bits for battery switchover.
BATPRG
Result
00
Battery switchover enabled on low V DD
01
Battery switchover enabled on low V DD and low V DCIN
1X 1
Battery switchover disabled
1
X = don’t care.
Table 20. Peripheral C onfiguration SFR (PERIPH, Address 0xF4)
Bit
7
6
Mnemonic
RX2FLAG
VSWSOURCE
Default
0
1
Description
If set, indicates that an RxD2 edge event has triggered wake-up from PSM2.
Indicates the power supply that is internally connected to V SWOUT .
0 = V SWOUT is connected to V BAT .
1 = V SWOUT is connected V DD .
5
4
VDD_OK
PLL_FLT
1
0
If set, indicates that the V DD power supply is ready for operation.
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (Bit 7) in the start
ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the PLL_FLT bit
(see Table 52).
3
REF_BAT_EN
0
Set this bit to enable the internal voltage reference in PSM2 mode. This bit should be set if LCD is on
in the PSM1 and PSM2 modes.
2
[1:0]
Reserved
RXPROG
0
0
This bit must be kept at 0 for proper operation.
Controls the function of the P0.7/SS/T1/RxD2 pin.
RXPROG
Result
00
GPIO
01
RxD2 with wake-up disabled
11
RxD2 with wake-up enabled
Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit
7
6
5
4
3
2
1
0
Mnemonic
EPSR
Reserved
ESAG
Reserved
EVADC
EBAT
EBSO
EVDCIN
Default
0
0
0
0
0
0
0
0
Description
Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
Reserved.
Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
This bit must be kept at 0 for proper operation.
Enables a PSM interrupt when the V DCIN ADC monitor interrupt flag (FVADC) is set.
Enables a PSM interrupt when the V BAT monitor interrupt flag (FBAT) is set.
Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
Enables a PSM interrupt when the V DCIN monitor interrupt flag (FVDCIN) is set.
Rev. D | Page 29 of 156
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