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| 型号： | ADE5166ASTZF62 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 93/156页 |
| 文件大小： | 0K |
| 描述： | IC METER/8052/RTC/LCD DRV 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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PSM
Data Sheet
INTERRUPT SYSTEM
The unique power management architecture of the ADE5166/
ADE5169/ADE5566/ADE5569 includes an operating mode
(PSM2) where the 8052 MCU core is shut down. Events can be
configured to wake the 8052 MCU core from the PSM2 operating
mode. A distinction is drawn here between events that can trigger
the wake-up of the 8052 MCU core and events that can trigger
an interrupt when the MCU core is active. Events that can wake
the core are referred to as wake-up events, whereas events that
can interrupt the program flow when the MCU is active are
called interrupts. See the 3.3 V Peripherals and Wake-Up Events
section to learn more about events that can wake the 8052 core
from PSM2 mode.
The ADE5166/ADE5169/ADE5566/ADE5569 provide 12 inter-
rupt sources with three priority levels. The power management
interrupt is at the highest priority level. The other two priority
levels are configurable through the interrupt priority SFR (IP,
Address 0xB8) and the Interrupt Enable and Priority 2 SFR
(IEIP2, Address 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The 8052 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
ADE5166/ADE5169/ADE5566/ADE5569
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed (see the
Interrupt Priority section).
INTERRUPT ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 possess advanced
power supply management features. To ensure a fast response to
time-critical power supply issues, such as a loss of line power,
the power supply management interrupt should be able to inter-
rupt any interrupt service routine. To enable the user to have full
use of the standard 8052 interrupt priority levels, an additional
priority level is added for the power supply management (PSM)
interrupt. The PSM interrupt is the only interrupt at this highest
interrupt priority level.
HIGH
PRIORITY 1
PRIORITY 0
LOW
Figure 88. Interrupt Architecture
HIGH
LOW
PRIORITY 1
PRIORITY 0
See the Power Supply Management (PSM) Interrupt section for
more information on the PSM interrupt.
Figure 87. Standard 8052 Interrupt Priority Levels
INTERRUPT REGISTERS
The control and configuration of the interrupt system are carried out via four interrupt-related SFRs, which are discussed in this section.
Table 80. Interrupt SFRs
SFR
IE
IP
IEIP2
WDCON
Address
0xA8
0xB8
0xA9
0xC0
Default
0x00
0x00
0xA0
0x10
Bit Addressable
Yes
Yes
No
Yes
Description
Interrupt enable (see Table 81).
Interrupt priority (see Table 82).
Interrupt Enable and Priority 2 (see Table 83).
Watchdog timer (see Table 88 and the Writing to the Watchdog Timer SFR
(WDCON, Address 0XC0) section).
Table 81. Interrupt Enable SFR (IE, Address 0xA8)
Bit
7
6
5
4
3
2
1
0
Bit Address
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
0xA8
Mnemonic
EA
ETEMP
ET2
ES
ET1
EX1
ET0
EX0
Description
Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.
Enables the temperature ADC interrupt. Set by the user.
Enables the Timer 2 interrupt. Set by the user.
Enables the UART serial port interrupt. Set by the user.
Enables the Timer 1 interrupt. Set by the user.
Enables the External Interrupt 1 (INT1). Set by the user.
Enables the Timer 0 interrupt. Set by the user.
Enables External Interrupt 0 (INT0). Set by the user.
Rev. D | Page 93 of 156
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADE5166ASTZF62-RL | 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5169 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
| ADE5169ASTZF62 | 功能描述:IC METER/8052/RTC/LCD DR 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5169ASTZF62-RL | 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5566 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
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