- 您现在的位置：买卖IC网 > PDF目录4596 > ADE5166ASTZF62 (Analog Devices Inc)IC METER/8052/RTC/LCD DRV 64LQFP PDF资料下载
参数资料
| 型号： | ADE5166ASTZF62 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 147/156页 |
| 文件大小： | 0K |
| 描述： | IC METER/8052/RTC/LCD DRV 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页当前第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页
Data Sheet
Table 159. I 2 C Interrupt Status SFR (SPI2CSTAT, Address 0xEA)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
7
6
Mnemonic
I2CBUSY
I2CNOACK
Default
0
0
Description
This bit is set to Logic 1 when the I 2 C interface is used. When set, the Tx FIFO is emptied.
I 2 C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device
does not send an acknowledgement. The I 2 C communication is stopped after this event.
Write a 0 to this bit to clear it.
5
I2CRxIRQ
0
I 2 C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
Write a 0 to this bit to clear it.
4
I2CTxIRQ
0
I 2 C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
Write a 0 to this bit to clear it.
[3:2]
I2CFIFOSTAT
00
Status bits for 3- or 4-byte deep I 2 C FIFO. The FIFO monitored in these two bits is the one currently
used in I 2 C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT
00
01
10
11
Result
FIFO empty
Reserved
FIFO half full
FIFO full
1
0
I2CACC_ERR
I2CTxWR_ERR
0
0
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when a write is attempted when the I 2 C transmit FIFO is full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
1
9
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
ACK BY
SLAVE
FRAME 2
ACK BY
MASTER
FRAME N + 1
NACK BY STOP BY
MASTER MASTER
SERIAL BUS ADDRESS BYTE
DATA BYTE 1 FROM MASTER
Figure 115. I 2 C Read Operation
DATA BYTE N FROM SLAVE
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
ACK BY
SLAVE
STOP BY
MASTER
Figure 116. I 2 C Write Operation
Figure 115 and Figure 116 depict I 2 C read and write operations,
respectively. Note that the LSB of the I2CADR SFR (Address 0xE9)
is used to select whether a read or write operation is performed
on the slave device. During the read operation, the master acknowl-
edgements are generated automatically by the I 2 C peripheral. The
master-generated no acknowledge (NACK) before the end of
a read operation is also automatically generated after the I2CRCT
bits in the I2CMOD SFR (Address 0xE8[4:0]) have been read from
the slave. If the I2CADR register is updated during a transmission,
the master generates a start condition instead of a stop at the end
Reading the SPI/I 2 C Receive Buffer SFR (SPI2CRx,
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx .
A 3-cycle instruction, such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
of the read or write operation and then continues with the next
communication.
Rev. D | Page 147 of 156
相关PDF资料 |
PDF描述 |
|---|---|
| NCP699SN28T1G | IC REG LDO 2.8V 240MA 5TSOP |
| RSC50DRYN-S13 | CONN EDGECARD 100POS .100 EXTEND |
| LFEC3E-4QN208I | IC FPGA 3.1KLUTS 208PQFP |
| KSZ8995MAI | IC SWITCH 5-PORT 10/100 128PQFP |
| MIC5281-3.3YMME TR | IC REG LDO 3.3V 25MA 8MSOP-EP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADE5166ASTZF62-RL | 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5169 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
| ADE5169ASTZF62 | 功能描述:IC METER/8052/RTC/LCD DR 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5169ASTZF62-RL | 功能描述:IC METER/8052/RTC/LCD DRV 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE5566 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
发布紧急采购，3分钟左右您将得到回复。