参数资料
型号: ADE5166ASTZF62
厂商: Analog Devices Inc
文件页数: 140/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘

ADE5166/ADE5169/ADE5566/ADE5569
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE5166/ADE5169/ADE5566/ADE5569 integrate a complete
hardware serial peripheral interface on chip. The SPI is full duplex
so that eight bits of data are synchronously transmitted and simul-
taneously received. This SPI implementation is double buffered,
allowing users to read the last byte of received data while a new
byte is shifted in. The next byte to be transmitted can be loaded
while the current byte is shifted out.
Data Sheet
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO/ZX),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
(P0.7/SS/T1/RxD2) pins, while the firmware interface is via the
SFRs listed in Table 150.
Note that the SPI pins are shared with the I 2 C pins. Therefore, the
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF[5]) selects which peri-
pheral is active.
SPI REGISTERS
Table 150. SPI SFR List
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Mnemonic
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPISTAT
R/W
W
R
R/W
R/W
R/W
Length (Bits)
8
8
8
8
8
Default
0
0
0x10
0
0
Description
SPI/I 2 C transmit buffer (see Table 151).
SPI/I 2 C receive buffer (see Table 152).
SPI Configuration SFR 1 (see Table 153).
SPI Configuration SFR 2 (see Table 154).
SPI interrupt status (see Table 155).
Table 151. SPI/I 2 C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
Bit
[7:0]
Mnemonic
SPI2CTx
Default
0
Description
SPI or I 2 C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I 2 C bus.
Table 152. SPI/I 2 C Receive Buffer SFR (SPI2CRx, Address 0x9B)
Bit
[7:0]
Mnemonic
SPI2CRx
Default
0
Description
SPI or I 2 C receive buffer. When the SPI2CRx SFR is read, one byte from the receive FIFO output is
transferred to the SPI2CRx SFR. A new data byte from the SPI or I 2 C bus is written to the FIFO input.
Rev. D | Page 140 of 156
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