参数资料
型号: ADE5166ASTZF62
厂商: Analog Devices Inc
文件页数: 141/156页
文件大小: 0K
描述: IC METER/8052/RTC/LCD DRV 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
Data Sheet
Table 153. SPI Configuration SFR 1 (SPIMOD1 , Address 0xE8)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
[7:6]
5
Bit Address
0xEF to 0xEE
0xED
Mnemonic
Reserved
INTMOD
Default
00
0
Description
Reserved.
SPI interrupt mode.
INTMOD
0
1
Result
SPI interrupt is set when the SPI Rx buffer is full
SPI interrupt is set when the SPI Tx buffer is empty
4
0xEC
AUTO_SS
1
SS output control (see Figure 112).
AUTO_SS
0
1
Result
The SS pin is held low while this bit is cleared, allowing manual chip select
control using the SS pin
Single byte read or write; the SS pin goes low during a single byte
transmission and then returns high
Continuous transfer; the SS pin goes low during the duration of the
multibyte continuous transfer and then returns high
3
0xEB
SS_EN
0
Slave mode, SS input enable.
When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the
SPI slave interface.
2
0xEA
RxOFW
0
Receive buffer overflow write enable.
RxOFW
0
1
Result
If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte is discarded
If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte overwrites the old data
[1:0]
0xE9 to 0xE8
SPIR
00
Master mode, SPI SCLK frequency.
SPIR
00
01
10
11
Result (f CORE = 4.096 MHz)
f CORE /8 = 512 kHz
f CORE /16 = 256 kHz
f CORE /32 = 128 kHz
f CORE /64 = 64 kHz
Rev. D | Page 141 of 156
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