参数资料
型号: ADE7518ASTZF16
厂商: Analog Devices Inc
文件页数: 78/128页
文件大小: 0K
描述: IC ENERGY METER MCU 16K 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
特色产品: ADE7518: Single-phase Energy-Measurement IC
标准包装: 160
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 797 (CN2011-ZH PDF)
ADE7518
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is loaded
into the program counter. When the interrupt service routine
is complete, the program counter is popped off the stack by a
RETI instruction. This allows program execution to resume
from where it was interrupted. The interrupt vector addresses
are shown in Table 64.
CONTEXT SAVING
When the 8052 vectors to an interrupt, only the program counter
is saved on the stack. Therefore, the interrupt service routine
must be written to ensure that registers used in the main
program are restored to their preinterrupt state. Common
registers that can be modified in the ISR are the accumulator
register and the PSW register. Any general-purpose registers
that are used as scratch pads in the ISR should also be restored
Table 64. Interrupt Vector Addresses
Source
IE0
TF0
Vector Address
0x0003
0x000B
before exiting the interrupt. The following example 8052 code
shows how to restore some commonly used registers:
GeneralISR:
; save the current accumulator value
IE1
0x0013
PUSH
ACC
TF1
RI + TI
0x001B
0x0023
; save the current status and register bank
selection
TF2 + EXF2
Reserved
0x002B
0x0033
PUSH
PSW
ISPI/I2CI
IPSM (Power Supply)
IADE (Energy Measurement DSP)
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
0x003B
0x0043
0x004B
0x0053
0x005B
; service interrupt
; restore the status and register bank
selection
INTERRUPT LATENCY
POP
PSW
The 8052 architecture requires that at least one instruction
; restore the accumulator
executes between interrupts. To ensure this, the 8052 MCU
core hardware prevents the program counter from jumping to
an ISR immediately after completing an RETI instruction or an
access of the IP and IE registers.
The shortest interrupt latency is 3.25 instruction cycles, 800 ns
with a clock of 4.096 MHz. The longest interrupt latency for a
high priority interrupt results when a pending interrupt is
generated during a low priority interrupt RETI, followed by a
multiply instruction. This results in a maximum interrupt
latency of 16.25 instruction cycles, 4 μs with a clock of 4.096 MHz.
Rev. 0 | Page 78 of 128
POP
RETI
ACC
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