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| 型号： | ADE7518ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 80/128页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 特色产品： | ADE7518: Single-phase Energy-Measurement IC |
| 标准包装： | 160 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
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ADE7518
Table 66. Watchdog and Flash Protectio n Byte in Flash (Flash Address = 0x3FFA)
Bit
7
Mnemonic
WDPROT_PROTKY7
Default
1
Description
This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key.
When this bit is cleared, the watchdog enable (WDE) and interrupt response bits (WDIR) cannot
be changed by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1.
The watchdog timeout in PRE[3:0] can still be modified by user code.
The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the
watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the
Protecting the Flash Memory section for more information on how to clear this bit).
6 to 0
PROTKY[6:0]
0xFF
These bits hold the flash protection key. The content of this flash address is compared to the
Flash Protection Key SFR (PROTKY, 0xBB) when the protection is being set or changed. If the two
values match, the new protection is written to Flash Address 0x3FFF to Flash Address 0x3FFB.
See the Protecting the Flash Memory section for more information on how to configure these bits.
Writing to the Watchdog Timer SFR (WDCON, 0xC0)
Writing data to the WDCON SFR involves a double instruction
sequence. The WDWR bit must be set and the following
instruction must be a write instruction to the WDCON SFR.
Disable Watch dog
CLR EA
SETB WDWR
CLR WDE
SETB EA
This sequence is necessary to protect the WDCON SFR from
code execution upsets that may unintentionally modify this
SFR. Interrupts should be disabled during this operation due to
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog timeout
period, a system reset occurs unless the watchdog timer interrupt
is enabled. The watchdog timer interrupt enable bit (WDIR) is
located in the Watchdog Timer SFR (WDCON, 0xC0). Enabling
the WDIR bit allows the program to examine the stack or other
variables that may have led the program to execute inappropriate
code. The watchdog timer interrupt also allows the watchdog to
be used as a long interval timer.
Note that WDIR is automatically configured as a high priority
interrupt. This interrupt cannot be disabled by the EA bit in the
IE register (see Table 58). Even if all of the other interrupts are
disabled, the watchdog is kept active to watch over the program.
the consecutive instruction cycles.
Rev. 0 | Page 80 of 128
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| ADE7518ASTZF16-RL | 功能描述:IC ENERGY METER MCU 16K 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
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| ADE7518ASTZF8-RL | 功能描述:IC ENERGY METER MCU 8K 64LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
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