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| 型号： | ADE7763ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/56页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 20SSOP |
| 标准包装： | 66 |
| 输入阻抗： | 390 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 3mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
| 配用： | EVAL-ADE7763ZEB-ND - BOARD EVALUATION FOR ADE7763 |
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ADE7763
LINE VOLTAGE SAG DETECTION
In addition to detecting the loss of the line voltage when there
are no zero crossings on the voltage channel, the ADE7763 can
also be programmed to detect when the absolute value of the line
voltage drops below a peak value for a specified number of line
Data Sheet
PEAK DETECTION
The ADE7763 can also be programmed to detect when the
absolute value of the voltage or current channel exceeds a
specified peak value. Figure 36 illustrates the behavior of the
peak detection for the voltage channel.
Both Channel 1 and Channel 2 are monitored at the same time.
FULL SCALE
SAGLVL[7:0]
SAG
CHANNEL 2
SAGCYC[7:0] = 0x04
3 LINE CYCLES
SAG RESET HIGH
WHEN CHANNEL 2
EXCEEDS SAGLVL[7:0]
V 2
VPKLVL[7:0]
PKV INTERRUPT
FLAG (BIT 8 OF
STATUS REGISTER)
READ RSTSTATUS
PKV RESET LOW
WHEN RSTSTATUS
REGISTER IS READ
Figure 35. Sag Detection
In Figure 35 the line voltage falls below a threshold that
has been set in the sag level register (SAGLVL[7:0]) for three
line cycles. The quantities 0 and 1 are not valid for the SAGCYC
register, and the contents represent one more than the desired
number of full line cycles. For example, if the DISSAG bit in the
mode register is Logic 0 and the sag cycl e register
(SAGCYC[7:0]) contains 0x04, the SAG pin goes active low at
the end of the third line cycle for which the line voltage
(Channel 2 signal) falls below the threshold. As is the case when
zero crossings are no longer detected, the sag event is also
recorded by setting the SAG flag in the interrupt status register.
If the SAG enable bit is set to Logic 1, the IRQ logi c output will
go active low—see the Interrupts section. The SAG pin goes
logic high again when the absolute value of the signal on Channel
2 exceeds the level set in the sag level register. This is shown in
cycle from the time when the signal on Channel 2 first dropped
below the threshold level.
Sag Level Set
The contents of the sag level register (1 byte) are compared to
the absolute value of the most significant byte output from
LPF1 after it is shifted left by one bit. For example, the nominal
maximum code from LPF1 with a full-scale signal on Channel 2
is 0x2518—see the Channel 2 Sampling section. Shifting one bit
left gives 0x4A30. Therefore, writing 0x4A to the SAG level
register puts the sag detection level at full scale. Writing 0x00 or
0x01 puts the sag detection level at 0. The SAG level register is
compared to the most significant byte of a waveform sample
after the shift left, and detection occurs when the contents of
the sag level register are greater.
REGISTER
Figure 36. Peak Level Detection
been set in the voltage peak register (VPKLVL[7:0]). The
voltage peak event is recorded by setting the PKV flag in the
interrupt status register. If the PKV enable bit is set to Logic 1 in
the interrupt mask register, the IRQ logic output will go active
low. Similarly, the current peak event is recorded by setting the
PKI flag in the interrupt status register—see the Interrupts
section.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are
compared to the absolute value of Channel 1 and Channel 2,
respectively, after they are multiplied by 2. For example, the
nominal maximum code from the Channel 1 ADC with a full-
scale signal is 0x2851EC—see the Channel 1 Sampling section.
Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to
the IPKLVL register, for example, puts the Channel 1 peak
detection level at full scale and sets the current peak detection
to its least sensitive value. Writing 0x00 puts the Channel 1
detection level at 0. Peak level detection is done by comparing
the contents of the IPKLVL register to the incoming Channel 1
sample. The IRQ pin indicates that the peak level is exceeded if
the PKI or PKV bits are set in the interrupt enable register
(IRQEN [15:0]) at Address 0x0A.
Peak Level Record
The ADE7763 records the maximum absolute value reached by
Channel 1 and Channel 2 in two different registers—IPEAK and
VPEAK, respectively. VPEAK and IPEAK are 24-bit, unsigned
registers. These registers are updated at a rate of CLKIN/4
regardless of the waveform sampling rate. The contents of the
VPEAK register correspond to two times the maximum absolute
value observed on the Channel 2 input. The contents of IPEAK
represent the maximum absolute value observed on the Channel 1
Rev. C | Page 18 of 56
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADE7763ARSZ | 制造商:Analog Devices 功能描述:IC, SINGLE PHASE ENERGY METER, SSOP-20 |
| ADE7763ARSZRL | 功能描述:IC ENERGY METERING 1PHASE 20SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE7763ARSZRL | 制造商:Analog Devices 功能描述:IC, SINGLE PHASE ENERGY METER, SSOP-20 |
| ADE7768 | 制造商:AD 制造商全称:Analog Devices 功能描述:Energy Metering IC with Integrated Oscillator and Positive Power Accumulation |
| ADE7768AR | 制造商:AD 制造商全称:Analog Devices 功能描述:Energy Metering IC with Integrated Oscillator and Positive Power Accumulation |
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