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参数资料
| 型号： | ADMC201 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 11/16页 |
| 文件大小： | 193K |
| 代理商： | ADMC201 |
ADMC201
REV. A
–11–
PHIP1/2/3
T he inputs for reverse vector transforma-
tion (Clarke and Park).
T hese registers contain the results
of the Clarke transformation that
are the inputs to the reverse Park rotation.
VX , VY contain the results of the forward
Park rotation.
RHOP is the angle used during the
forward vector transformation. Writing to
the RHOP register causes the forward
rotation to start based on values in
RHOP, VD and VQ registers.
RHO is the angle used during the reverse
vector transformation. Writing to this
register starts the reverse rotation using
the values in the RHO, PHIP1/2/3
registers.
RHO and RHOP are unsigned ratios of
360
°
. For example, 45 degrees would be
45/360
×
2
12
.
Write to this register to change the
digital outputs and read from it to
determine the state of digital inputs.
T his register is used to configure the
digital I/O as input or output and to
enable interrupt on change of state.
IX /IY
VX , VY
RHOP
RHO
PIODAT A
PIOCT RL
DE SCRIPT ION OF T HE RE GIST E RS
All unspecified register locations are reserved.
SYSCT RL
System Control Register (See T ables V,
VI, VII).
SYSST AT
System Status Register (See T able VII).
ADCU
T hese registers contain the results from
ADCV
the first three analog input channels
ADCW
U, V, and W. T he output data format
is twos complement and, therefore, Bit 0
is always zero as the A/D converter
has 11-bit resolution.
ADCAUX
T his register contains the conversion result
of the auxiliary channels AUX 0, AUX 1,
AUX 2 or AUX 3.
PWMT M
PWM Master Switching Period
PWMCHA
PWM Channel A On-T ime
PWMCHB
PWM Channel B On-T ime
PWMCHC
PWM Channel C On-T ime
PWMDT
PWM Programmable Deadtime Value
PWMPD
PWM Programmable Pulse Deletion Value
ID/IQ
T hese are the results of the reverse
rotation (torque and flux components).
PHV1/2/3
T hese are the results from the forward
Clarke T ransformation.
EN
ADDRESS
DECODE
V
DD
IS
INTn
STRB
R/W
CLKOUT1
D0–D15
A0–A15
TMS320C20
TMS320C25
TMS320C25-50
CS
IRQ
RD
WR
CLK
D0–D11
A0–A3
ADMC201
ADDRESS BUS
DATA BUS
Figure 12. TI Second Generation Devices TMS320C20/
C25/C25–50
In the case of the ADSP-2171/2181, the system clock is inter-
nally scaled, a 10 MHz system clock will derive a 20 MHz
CLK OUT . In the case of the T MS320C2X , the CLK OUT 1
signal is derived from the system clock divided by a factor of 4,
consequently a 50 MHz T MS320C25-50 will derive a
12.5 MHz CLK OUT 1 for use by the ADMC201.
Note: a pull-up resistor is required on the IRQ (Pin 18) output
from the ADMC201. T he ST OP (Pin 47) must be tied low if
not in use.
RE GIST E R ADDRE SSING
Four address lines (A0 through A3) are used in conjunction
with the control lines (
CS,
WR
,
RD
,) to select registers 0
through 15. T he
CS
and
RD
control lines are active low. T he
registers are given symbolic names.
T able II.
Pin
Function
CS
Enables the ADMC201 register interface
(connect via chip select logic-active low)
Places data from the internal register onto the
data bus
Loads the internal register with data on the
data bus on its positive edge
RD
WR
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