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参数资料
| 型号： | ADMC201 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 14/16页 |
| 文件大小： | 193K |
| 代理商： | ADMC201 |
ADMC201
REV. A
–14–
T able VIII. System Status Register (SYSST AT )
1
RESET
Default
Bit
Function
0
A/D Conversion
Completion Interrupt
(1 = T rue)
Vector T ransformation
Completion Interrupt
(1 = T rue)
Digital I/O Change of State
Interrupt (1 = T rue)
Rotation Results are Valid
(1 = Valid)
IRQ
Generated from T his
Device (1 = T rue)
0
1
0
2
0
4
X
2
0
11
NOT ES
1
Reading this register clears the interrupt status flags Bits 0, 1, 2 and 11.
2
Undefined until the first Vector T ransformation has started
Bit 0
A/D Conversion Completion Interrupt. T his register
is set to 1 when the A/D conversion process has com-
pleted and ADC interrupts have been enabled in the
SYSCT RL register.
Bit 1
Interrupt Status. T his register is set to 1 when the
Vector T ransformation is completed and the Vector
T ransformation completion interrupts have been
enabled.
Bit 4
T his bit is set to 1 when the rotation results are valid
reading this.
Bit 11
If any interrupt source on the ADMC201 occurs, then
this bit is set to 1.
T able IX . Programmable Digital I/O Control Register
(PIOC T RL)
Reset
Default
Bit
Function
0
Programmable Digital I/O Direction
Bit 0 (0 = Input, 1 = Output)
Programmable Digital I/O Direction
Bit 1 (0 = Input, 1 = Output)
Programmable Digital I/O Direction
Bit 2 (0 = Input, 1 = Output)
Programmable Digital I/O Direction
Bit 3 (0 = Input, 1 = Output)
Programmable Digital I/O Direction
Bit 4 (0 = Input, 1 = Output)
Programmable Digital I/O Direction
Bit 5 (0 = Input, 1 = Output)
Programmable Digital I/O Bit 0 Interrupt
(0 = Disable, 1 = Enable)
Programmable Digital I/O Bit 1 Interrupt
(0 = Disable, 1 = Enable)
Programmable Digital I/O Bit 2 Interrupt
(0 = Disable, 1 = Enable)
Programmable Digital I/O Bit 3 Interrupt
(0 = Disable, 1 = Enable)
Programmable Digital I/O Bit 4 Interrupt
(0 = Disable, 1 = Enable)
Programmable Digital I/O Bit 5 Interrupt
(0 = Disable, 1 = Enable)
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
Bit 0–5
Sets corresponding Digital I/O bits as either input
or output.
Configures Digital I/O Bits 0–5 as interrupt on
change of state sources. Enabling interrupts for bits
configured as output has no effect.
Bit 6–11
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