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参数资料
| 型号： | ADMC201 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 3/16页 |
| 文件大小： | 193K |
| 代理商： | ADMC201 |
ADMC201
REV. A
–3–
T able I. ADMC201 T iming Specifications (V
DD
= 5 V,
6
5%; T
A
= –4
0
8
C to +85
8
C)
Number
Symbol
ADMC201 T iming Requirements
Min
Max
Units
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
t
per
clk
t
pwh
clk
t
pwl
clk
t
su
csb_wrb
t
su
addr_wrb
t
su
data_wrb
t
hd
wrb_data
t
hd
wrb_addr
t
hd
wrb_csb
t
pwl
wrb
1
t
pwh
wrb
1
t
hd
wrb_clk_h
1
t
su
wrb_clk_h
1
t
su
wrb_clk_l
1
t
hd
clk_wrb_l
1
t
su
csb_rdb
t
su
addr_rdb
t
hd
rdb_addr
t
hd
rdb_csb
t
pwl
rdb
t
pwh
rdb
t
su
rdb_clk_h
t
hd
rdb_clk_h
t
pwl
resetb
CLK Period
CLK Pulse Width, High
CLK Pulse Width, Low
CS
Low before Falling Edge of
WR
ADDR Valid before Falling Edge of
WR
DAT A Valid before Rising Edge of
WR
DAT A Hold after Rising Edge of
WR
ADDR Hold after Rising Edge of
WR
CS
Hold after Rising Edge of
WR
WR
Pulse Width, Low
WR
Pulse Width, High
WR
Low after Rising Edge of CLK
WR
High before Rising Edge of CLK
WR
High before Falling Edge of CLK
WR
High after Falling Edge of CLK
CS
Low before Falling Edge of
RD
ADDR Valid before Falling Edge of
RD
ADDR Hold after Rising Edge of
RD
CS
Hold after Rising Edge of
RD
RD
Pulse Width, Low
RD
Pulse Width, High
RD
Low before Rising Edge of CLK
RD
Low after Rising Edge of CLK
RESET
Pulse Width, Low
40
20
20
0
0
13
4.5
4.5
4.5
20
20
7
7
10
10
0
0
0
0
20
20
7.5
7.5
2
×
t
per
clk
160
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOT E
1
All WRIT ES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).
Number
Symbol
ADMC201 Switching Characteristics
Min
Max
Units
25
26
27
28
t
dly
rdb_data
t
hd
rdb_data
t
pwh
_pio
t
pwl
_pio
DAT A Valid after Falling Edge of
RD
DAT A Hold after Rising Edge of
RD
Digital I/O Pulse Width, High
Digital I/O Pulse Width, Low
-
0
2
×
t
per
clk
2
×
t
per
clk
23
-
-
-
ns
ns
ns
ns
11
4
5
6
7
10
12
15
13
9
8
14
CLK
CS
A0–A3
WR
DATA
NOTE:
ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN
ONE SYSTEM CLOCK CYCLE (i.e. 0 WAIT STATES)
Figure 3. Write Cycle Timing Diagram
1
2
3
CLK
Figure 1. Clock Input Timing
24
CLK
RESET
Figure 2. Reset Input Timing
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| ADMC201AP | 制造商:Analog Devices 功能描述: |
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